Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2003-04-28
2004-07-06
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S500000, C713S502000, C713S002000
Reexamination Certificate
active
06760854
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to enhancing time resynchronization at a integrated circuit serial interface.
2. Description of the Related Art
Timing of clock pulses received at a serial port or interface may, from time to time, lose synchronization with the timing of clock pulses received or generated at a microprocessor with which the interface is associated. When time synchronization is lost at an interface, the controller often does not become promptly aware of this loss, with the result that the interface operates without synchronization to the remainder of the system for many cycles. Where timing differences of one or more cycles are critical and synchronization is lost at an interface, the system controller may refuse to recognize or respond to signals from such an interface.
What is needed is an approach that promptly allows the serial interface to advise the microprocessor if the interface timing is not synchronized to the microprocessor timing, and to allow the microprocessor to promptly resynchronize the timing of the interface, if resynchronization is needed. Preferably, the approach should facilitate timing resynchronization, if desired, after each command is received by the serial interface.
SUMMARY OF THE INVENTION
These needs are met by the invention, which uses an input serial interface and an output serial interface, whose operations are synchronized, to perform certain operations in tandem and to thus achieve some of the benefits of a parallel port or interface, such as faster processing of groups of bits representing a digital signal. In one embodiment, each time, or at selected times, the serial interface receives a command, the interface determines whether the command is a valid command, by comparing the bit pattern provided by the microprocessor with the bit patterns understood by the serial interface itself. If the received command is not a valid command, because the bit pattern does not match at least one stored template, the serial interface communicates a unique signal indicating that this mismatch has occurred to the microprocessor, which then issues a Timing Resynchronization command to the serial interface.
REFERENCES:
patent: 4396995 (1983-08-01), Grau
patent: 4602327 (1986-07-01), LaViolette et al.
patent: 5016162 (1991-05-01), Epstein et al.
patent: 5428645 (1995-06-01), Dolev et al.
patent: 5440746 (1995-08-01), Lentz
patent: 5680537 (1997-10-01), Byers et al.
patent: 5818885 (1998-10-01), Kim
patent: 5845239 (1998-12-01), Laczko, Sr. et al.
patent: 6028675 (2000-02-01), Fields et al.
patent: 6061822 (2000-05-01), Meyer
patent: 6434612 (2002-08-01), Hughes et al.
patent: 6470458 (2002-10-01), Dreps et al.
patent: 02003850 (1990-01-01), None
patent: 09179793 (1997-07-01), None
Casale et al., “An efficient synchronization method for dual bus networks”, Global Telecom. Conf., 1989, and Exhibition. ‘Communications Technology for the 1990s and Beyond’. GLOBECOM '89., IEEE , Nov. 27-30, 1989, Page(s): 548-553 vol. 1.
Cirrus Logic Inc.
Lee Thomas
Lin, Esq. Steven
Trujillo James K.
LandOfFree
Method and apparatus for handling a framing error at a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for handling a framing error at a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for handling a framing error at a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3251212