Low dose super deep source/drain implant

Details Low dose super deep source/drain implant Low dose super deep source/drain implant

2002-08-29

2004-07-27

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S216000, C438S286000, C438S261000

Reexamination Certificate

active

06767778

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a semiconductor device having reduced junction capacitance by an additional low dose super deep source/drain implant, and to a method for fabricating such a device.
As the semiconductor industry progresses to even smaller sub-micron dimensions, continued advances in manufacturing techniques are required to provide submicron semiconductor devices with acceptable electrical characteristics. As CMOS gate lengths are reduced, the risk of a short-channel effect, called punch-through, rises. Punch-through is a circuit breakdown in which the drain voltage reaches a sufficiently large value that the depletion layer associated with the drain spreads across the substrate and reaches the source. This causes a destructive source/drain conduction path or leakage current.
Various approaches have been taken to avoid short-channel effects. One technique for avoiding punch-through is to raise the well or substrate dopant concentration, reducing the size of the depletion region so that punch-through does not occur when a voltage is applied. However, increasing the well concentration has drawbacks. The high substrate doping level causes a high source/drain junction capacitance, a low junction breakdown voltage, an increase in transistor threshold voltage, and high body effects. Furthermore, a high well concentration reduces carrier mobility, leading to a lowering of drive current.
Anti-punchthrough (APT) implants have been developed as an alternative to raising the dopant concentration generally throughout the well or substrate. APT implants increase dopant concentrations only near the channel and source/drain region, not throughout the entire substrate. Examples of such APT implants are halo implants and pocket implants, which are illustrated by FIG.
1
.
Over a semiconductor substrate
10
, a polycide gate
11
is formed. Heavily doped source and drain (HDD) regions
24
and lightly doped source and drain (LDD) regions
30
have been implanted. On a respective side of the polycide gate
11
, for convenience of illustration, there is either a halo implant
17
or a pocket implant
34
. The halo implant
17
is a self-aligned implant in which the polycide gate
11
acts as a mask during implant. The halo implant
17
is performed with a dopant opposite to that of the implant in the LDD regions
30
. As illustrated, the halo implant
17
is deeper both vertically and laterally than its respective LDD region
30
.
The pocket implant
34
is also a self-aligned implant in which a small pocket of a heavy dopant concentration is formed adjacent the LDD regions
30
to block the potential leakage path while allowing the channel region
15
to maintain a lower dopant concentration. In particular, the pocket implant
34
raises dopant concentrations only where the increased doping is needed, rather than raising the well concentration uniformly throughout the substrate
10
, as is the case with the halo implant
17
.
However, providing a pocket implant under the LDD regions by conventionally known methods, such as disclosed by U.S. Pat. No. 5,595,919, is both complicated and expensive by requiring additional processing steps, which adds production cost to the integrated circuit device. Accordingly, the present inventors have recognized a need for further improvements in semiconductor processing to provide reduce junction capacitance in the fabrication of integrated circuits by less complicated methods, requiring fewer processing steps, thereby reducing production costs.
SUMMARY OF THE INVENTION
The present invention is a sub-micron semiconductor device addressing junction capacitance through the use of a super deep but low dose source/drain implant performed in addition to source/drain implantation as well as a method of fabricating such a device. The super deep source/drain implant (i.e., implantation greater than about 0.25 &mgr;m) is performed after spacer formation to significantly reduce junction capacitance in the channel region. Although junction depth increases, there is a de minimis effect on the channel such that device performance is not sacrificed by the low dose super deep implant. The implantation process of the present invention may be applied to both n-channel and p-channel transistors.
In accordance with one embodiment, a method for fabricating semiconductor devices comprises providing a substrate, forming active areas on the substrate, isolating the active areas with a field oxide, and forming polycide gates having spacers in the active areas. The method further comprises implanting a first dopant at low energy into the substrate. The first dopant has a dosage sufficient to form a heavily doped source/drain region in the substrate adjacent the nitride spacers. The method further comprises implanting a second dopant comprising the same conductivity type as the first dopant but at a lower dosage and with greater energy to form a deeper lightly doped source/drain region in the substrate below the heavily doped source/drain region. Continuing processing is performed to form an active semiconductor device in the active areas.
In another embodiment of the invention, a method of fabricating an integrated circuit device having reduced junction capacitance comprises providing a layer of a field oxide over the surface of a semiconductor substrate, forming a gate electrode overlying the field oxide layer, and forming a silicon oxide layer having sidewalls on the surface and sidewalls of the gate electrode. The method further comprises forming silicon nitride spacers on the sidewalls of the silicon oxide sidewall layer, and implanting first ions having a first dosage and a first energy into the substrate to form a heavily doped source/drain region in the substrate adjacent the silicon nitride spacers. The method further comprises implanting second ions having the same conductivity type as the first ions, but at a second dosage lower than the first dosage and with a second energy greater than the first energy, to form a deeper lightly doped source/drain region in the substrate below the heavily doped source/drain region. The method further comprises annealing the substrate, and removing the silicon nitride spacers. The method further comprises implanting third ions with a third dosage at a third energy into the substrate to form lightly doped regions in the semiconductor substrate. Continuing processing is performed to fabricate the integrated circuit device.
In still other embodiment of the invention, a method of fabricating an integrated circuit device having reduced junction capacitance comprises providing a layer of a gate oxide over the surface of a semiconductor substrate. A gate electrode is formed overlying the gate oxide layer. The method further comprises forming a silicon oxide layer having sidewalls on the surface and sidewalls of the gate electrode, and implanting first ions with a first dosage at a first energy into the substrate to form lightly doped regions in the semiconductor substrate adjacent the gate electrode. The method further comprises forming silicon nitride spacers on the sidewalls of the silicon oxide sidewall layer, and implanting second ions having a second dosage and at a second energy into the substrate to form a heavily doped source/drain region in the substrate adjacent the silicon nitride spacers. Third ions are implanted having the same conductivity type as the first ions but at a third dosage lower than the second dosage and with a third energy greater than the third energy to form a deeper lightly doped source/drain region in the substrate below the heavily doped source/drain region. The method further comprises annealing the substrate, and continuing processing to fabricate the integrated circuit device.
In yet another embodiment, an integrated circuit device having reduced junction capacitance comprises a gate electrode overlying a gate silicon oxide layer on a surface of a semiconductor substrate, a silicon oxide layer lying on a surf

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