Method of forming source/drain regions in a semiconductor...

Details Method of forming source/drain regions in a semiconductor... Method of forming source/drain regions in a semiconductor...

2002-01-29

2004-04-13

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S229000, C438S230000, C438S231000, C438S299000, C438S301000, C438S303000, C438S307000, C438S595000

Reexamination Certificate

active

06720227

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to semiconductor processing, and, more particularly, to a method of forming source/drain regions in a semiconductor device.
2. Description of the Related Art
By way of background,
FIGS. 1A and 1B
depict an illustrative, partially complete, NMOS field effect transistor
10
formed above a surface
14
of a semiconducting substrate
12
between trench isolation regions
25
. At this stage of fabrication, the transistor
10
is comprised of a gate insulation layer
16
and a gate electrode
18
. Ultimately, as shown in
FIG. 1B
, source/drain regions
28
will be formed in the substrate
12
adjacent the gate electrode
18
.
FIGS. 1A and 1B
depict one illustrative prior art process flow for forming source/drain regions
28
in a semiconductor device. As shown therein, the process typically involves performing a first ion implantation process
13
to form doped regions
15
in the substrate. This implant is commonly referred to as an extension implant since it will become an extension of the completed source/drain region. Note that, on at least the illustrative NMOS device depicted in
FIG. 1A
, this extension implant
13
is generally self-aligned with respect to the gate electrode
18
. The dopant concentration of this initial implant process ranges from approximately 1×10
14
to 5×10
15
ions/cm
2
of the appropriate dopant atoms for the technology under consideration, e.g., arsenic or phosphorous for NMOS technology, boron for PMOS technology, etc, and at an energy level ranging from approximately 1-20 keV.
Thereafter, as shown in
FIG. 1B
, sidewall spacers
20
are formed adjacent the gate electrode
18
by depositing a layer of spacer material and performing an anisotropic etching process. Next, a second ion implantation process
17
is performed to form implant regions
19
in the substrate
12
. This second implant
17
is commonly referred to as the source/drain implant because it constitutes the bulk of the completed source/drain regions
28
of the device. The source/drain implant
17
is typically generally self-aligned with respect to the sidewall spacer
20
. The source/drain implant
17
may be performed with a dopant concentration ranging from approximately 5×10
14
to 5×10
15
ions/cm
2
and at an energy level ranging from approximately 20-40 keV. Thereafter, the device is subjected to one or more anneal processes to activate the implanted dopant atoms and to repair any damage to the lattice structure of the silicon resulting from the ion implantation process as described above. During this anneal process, the dopant atoms will migrate, or move, from their implanted position, although this is not indicated in
FIG. 1A
or
1
B. This dopant migration tends to be isotropic in direction, although such movement is not depicted in FIG.
1
B.
One problem found in modern semiconductor devices is known as off-state leakage currents. That is, as the name implies, when the transistor is “off,” i.e., when there is approximately zero volts applied to the gate electrode
18
of an NMOS device, some small current still flows between the source/drain regions
28
of the device. Such off-state leakage currents are problematic in that they unnecessarily consume power while not serving any useful function. This is particularly problematic in modem portable devices where power consumption is of key concern. Off-state leakage currents may also result in excessive chip heat, requiring heat sinks, fans, or other cooling devices.
There are several concerns with respect to the formation of source/drain regions
28
, and, in particular, to the formation of the source/drain extensions using the prior art process described above. In general, the more shallow the source/drain extension implant, the better the device will perform from a leakage perspective. However, all other things being equal, the more shallow the depth of the source/drain extension implant, the greater the resistance of the source/drain extension to electron flow. The increase in resistance is undesirable from an operational point of view as it would produce a slower chip. Conversely, if the source/drain extensions are made too deep in an effort to reduce the resistance, off-state leakage currents tend to increase.
The present invention is directed to a method that solves or reduces some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
A method of forming source/drain regions in a semiconductor device is provided. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, forming source/drain regions in the substrate adjacent the gate electrode by performing at least the following steps: performing two ion implantation processes to form source/drain extensions for the device and performing a third ion implantation process to further form source/drain regions for the device. Various N-type and P-type dopant atoms such as arsenic, phosphorous, boron and boron difluoride may be used with the present invention.


REFERENCES:
patent: 5308780 (1994-05-01), Chou et al.
patent: 6025239 (2000-02-01), Yu
patent: 6060364 (2000-05-01), Maszara et al.
patent: 6204138 (2001-03-01), Krishnan et al.
patent: 6211023 (2001-04-01), Yeh et al.

Affiliated with

Also associated with

Rating

Method of forming source/drain regions in a semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming source/drain regions in a semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming source/drain regions in a semiconductor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3247070