Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-09
2004-07-20
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S184000, C438S299000, C438S320000, C438S339000, C438S366000
Reexamination Certificate
active
06764893
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a semiconductor device capable of reducing a parasite capacitance of a semiconductive memory cell.
DESCRIPTION OF RELATED ARTS
As integration of a semiconductor device has been more enhanced, it becomes more difficult to obtain an overlay accuracy and a process margin with respect to a pattern formation process through the use of a photo registry. Hence, a self align contact (hereinafter referred as to SAC) process is specifically adapted and applied to solve these problems. The SAC process is an etching process that etches an object by using a previously deposited material itself instead of using an additional mask. Because of this characteristic, the SAC process reduces remarkably costs related to a fabrication of a semiconductor device. The SAC process itself uses several methods for achieving an effective etching, and a nitride layer is representatively used as an etching barrier among those various methods.
Therefore, the SAC etching process first encompasses lateral and top parts of a conductive pattern including a gate electrode and so forth with the nitride layer and etches an insulation layer under a condition in that an oxide layer is etched faster than the nitride layer.
Meanwhile, a polysilicon nitride layer and a polysilicon oxide layer are representatives of the nitride layer and the oxide layer, respectively. Particularly, the polysilicon nitride layer of which dielectric constant is approximately 7.5 has a higher dielectric constant than a polysilicon oxide layer of which dielectric constant is approximately 3.9.
A plug structure that uses a contact hole, which is formed by the SAC process, is applied to a semiconductive memory device such as a dynamic random access memory (DRAM). For instance, in case that a capacitor hole is formed by the SAC process with respect to a bit line, i.e., in case that the SAC process forms the capacitor hole by etching spaces between the bit lines, the bit line and the capacitor contact plug, that is, capacitance of the bit line is increased more than a conventional contact structure wherein a charge storage electrode is insulated with the oxide layer, e.g., the polysilicon oxide layer. However, the increase of the bit line capacitance becomes a factor for decreasing the capacitance of a cell.
There have been numerous attempts to overcome a problem of the decrease in the cell capacitance due to the nitride layer applied in accordance with the SAC process.
FIG. 1
is a cross-sectional view illustrating a semiconductor device fabricated in accordance with a conventional method suggested for solving the problem of the decrease in the cell capacitance due to the SAC process.
Referring to
FIG. 1
, a conductive pattern
13
including a mask layer
12
constructed with a silicon nitride layer and overlies a conductive layer
11
and a metal layer
11
constructed with polysilicon, tungsten (W), titanium (Ti) or titanium nitride (TiN) is formed on a substrate board
10
. Especially, the conductive pattern
13
is patterned in a line form being spaced out with a predetermined distance S between the conductive patterns
13
.
On lateral sides of each conductive pattern
13
, a dual spacer including a silicon oxide layer spacer
14
and a silicon nitride layer spacer
15
is formed. The silicon oxide layer spacer
14
is particularly formed with a height lower than a top part of the mask layer
12
using the silicon nitride layer to expose partially top portions of the lateral sides of the conductive pattern
13
. The silicon nitride layer spacer
15
is an outer spacer of the dual spacer structure being formed continuously on the exposed lateral portions of the conductive pattern
13
and the silicon oxide layer spacer
14
.
The silicon oxide layer spacer
14
, as the name itself indicates, is constructed with the silicon oxide layer deposited through a chemical vapor deposition (hereinafter referred as to CVD) technique until having a thickness greater than approximately 300 Å measured from the top portion of the mask layer
12
to that of the silicon oxide layer spacer
14
. Also, it is alternatively possible to form the top portion of the silicon oxide layer spacer
14
to be lower than a bottom portion of the mask layer
12
.
On the conductive pattern
13
and the substrate
10
, an insulation layer
16
constructed with a silicon oxide layer possessing a SAC contact hole is formed. The insulation layer is partially expanded onto the top portion of each conductive pattern
13
and exposes the silicon nitride layer spacer
15
allocated within the predetermined distance S between the conductive patterns
13
.
The SAC contact hole is filled with a plug
17
and self-aligned on the conductive pattern
13
, forming a SAC structure. The plug
17
, in addition to the above-described form, can be patterned with a preset patterning form through a conventional photo etching process.
In accordance with the conventional method as describe above, the conductive pattern, for instance, the dual spacer including the silicon oxide layer spacer and the silicon nitride layer spacer is formed on the lateral sides of the bit line. The dual spacer structure makes it possible to reduce the loading capacitance between the conductive layer and plug within the SAC contact hole, because the lateral sides of the conductive layer is encompassed with the silicon oxide layer spacer having a low dielectric constant.
However, in the Korean Patent Application Laid-Open No. 2000-0048819 suggested for embodying the method illustrated in
FIG. 1
, there is discovered a difficulty in forming each conductive pattern, e.g., a silicon oxide layer spacer on lateral sides of a bit line, of which height is lower than a top portion of the mask layer constructed with a silicon nitride layer since a selection ratio between the silicon oxide layer and the silicon nitride layer is not high in an actually practiced wafer having a micro-shape. In other words, the mask layer constructed with the silicon nitride layer is inevitably damaged during procedure proceedings, and thus, it is impossible to be applicable for a practical process.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device capable of preventing losses of a mask layer constructed with a silicon nitride layer when forming a dual spacer for reducing loading capacitance including a silicon oxide layer and a silicon nitride layer spacers.
In accordance with an aspect of the present invention, there is provided a method for a method for fabricating a semiconductor device, including the steps of: forming a plurality of patterns on a substrate, wherein the patterns are formed by stacking and patterning a first conductive layer, a silicon nitride mask layer and a metal mask layer on the substrate; depositing a first silicon oxide layer along the profile containing the patterns; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer, wherein the metal mask layer prevents losses of the silicon nitride mask layer; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming a self-align contact hole that is partially expanded to the top portion of the patterns; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer.
In accordance with another aspect of the present invention, there is also provided a method for a method for fabricating a s
Kim Dong-Sauk
Lee Sung-Kwon
Birch & Stewart Kolasch & Birch, LLP
Fourson George
Hynix / Semiconductor Inc.
Pham Thanh V
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