Protective hardmask for producing interconnect structures

Details Protective hardmask for producing interconnect structures Protective hardmask for producing interconnect structures

2000-04-17

2004-04-13

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S633000, C438S634000, C438S636000, C438S637000, C438S692000, C438S740000

Reexamination Certificate

active

06720249

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device having an overall reduced dielectric constant and a method of producing the device utilizing a series of hardmask layers which protect an interlevel dielectric material of the device.
2. Description of Related Art
As semiconductor devices decrease in feature size, line-to-line capacitance becomes a problem. When metal lines of a semiconductor device are patterned closer and closer together, the dielectric constant k of any interlayer dielectric (ILD) material needs to be reduced in order to reduce the capacitive coupling between those lines. Thus, it is preferable to use an ILD having as low a dielectric constant as possible. However, during formation of the interconnects within the semiconductor device, even a desirably low k ILD is subject to processing conditions which may undesirably increase its dielectric constant thereby increasing the overall effective dielectric constant of the device as a whole. During removal of excess metal used to form the interconnect by chemical mechanical planarization (CMP), the CMP slurry may contaminate or deteriorate the low k ILD. During the deposition of hardmasks and caps, the deposition processes may degrade the low-k ILD.
Damascene processes are one way to provide a method of forming interconnect structures to connect the numerous layers of metallization. A typical single damascene processes is described in U.S. Pat. No. 4,944,836 issued to Beyer which is incorporated herein by reference. A dual damascene process in which conductive lines and stud via metal contacts are formed simultaneously is described in U.S. Pat. No. 4,789,648 issued to Chow which is incorporated herein by reference.
Conventional methods for depositing a low-k organosilicate (OSG) hardmask over an ILD during damascene processes utilize a reactive precursor or precursor mix such as silane (SiH
4
), methylsilane (CH
3
SiH
3
), trimethylsilane ((CH
3
)
3
SiH), or tetramethylsilane ((CH
3
)
4
Si), and an oxidizer such as N
2
O, O
2
, CO, CO
2
, or H
2
O. However, the reactive oxygen content of the plasmas required to produce a low-k hardmask from these species is sufficient to damage bulk low-k ILD
30
, to damage and degrade adhesion between a hardmask and the ILD, or to alter the cladding/passivation layers present within the pores of nanoporous materials such as Nanoglass™ (Allied Signal, Santa Clara, Calif.).
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of protecting a low k ILD during semiconductor processing to preserve the low overall effective dielectric constant of the resultant device.
It is another object of the present invention to provide a method of forming interconnect structures in a semiconductor device wherein the low k ILD does not suffer any undesirable increases in its dielectric constant.
A further object of the invention is to provide a semiconductor device having a low overall effective dielectric constant.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of protecting a low dielectric constant layer on a semiconductor material during processing of the material, the method comprising: providing a substrate of a semiconductor material and, optionally, an etch stop layer thereover; depositing a bulk low dielectric constant material over the semiconductor material; depositing a first hardmask layer comprising a low dielectric constant material over the bulk low dielectric constant material; depositing a sacrificial second hardmask layer disposed over the first hardmask layer; subsequently processing the semiconductor material, the hardmask layers and the bulk low dielectric constant material; and removing the second hardmask layer while permanently retaining the first hardmask layer over the bulk low dielectric constant material, wherein the first hardmask layer material protects the bulk low dielectric constant material to substantially prevent alteration of the dielectric constant thereof during subsequent processing.
Preferably, the step of depositing a first hardmask layer comprises depositing a low dielectric constant material having a dielectric constant of about 2.5-8.0, preferably 2.5-4.5. Preferably, the step of depositing the first and second hardmask layers comprises depositing silicon nitride, silicon carbide, amorphous hydrogenated silicon carbide, silicon carbide nitride, organo-silicate glass, silicon rich oxide, silicon dioxide, tetraethylorthosilicate, phosphosilicate glass, organic siloxane polymer, carbon doped silicate glass, hydrogen doped silicate glass, silsesquioxane glass, spin-on glass, or fluorinated silicate glass.
The method of this aspect may further include the step of depositing a sacrificial third hardmask layer over the sacrificial second hardmask layer, the third hardmask layer being removed during subsequent processing. Preferably, the step of subsequent processing to make interconnect structures comprises forming openings in the hardmask layers and in the bulk low dielectric material and filling such openings with a metal to make electrically conductive connections from the substrate to a region above the first hardmask layer. Chemical mechanical polishing may be used to remove excess metal within the interconnect structures wherein the bulk low dielectric constant material is protected by the first hardmask layer from an undesirable increase in its dielectric constant, an undesirable increase in leakage, and yield reduction due to scratching.
The step of depositing the first and second hardmask layers may comprise a single deposition utilizing one precursor material and altering deposition conditions to provide two films with different dielectric constants. Preferably, the current aspect may further include an embedded etch stop layer dividing the bulk low dielectric constant material into a lower portion and an upper portion. Alternatively, the embedded etch stop layer may separate a bulk low dielectric constant material comprising two different types of material.
In a second aspect, the present invention is directed to a method of forming interconnect structures comprising the steps of: providing a semiconductor substrate; depositing a bulk dielectric material over the semiconductor substrate; depositing a first hardmask layer having a dielectric constant substantially equal to a dielectric constant of the bulk dielectric material; depositing a second hardmask layer over the first hardmask layer; depositing a third hardmask layer over the second hardmask layer; etching one or more vias and/or lines through the hardmask layers and the bulk dielectric material; depositing a conductive material into the vias; removing an excess of the conductive material by chemical mechanical planarization wherein the third and second hardmask layers are simultaneously removed; and retaining the first hardmask layer.
In a third aspect, the present invention is directed to an intermediate semiconductor device wherein a bulk dielectric material is protected from undesirable alteration of its dielectric constant comprising: a substrate; a bulk dielectric material disposed thereover; a first hardmask layer having a substantially similar dielectric constant as the bulk dielectric disposed over the bulk dielectric material; and a second hardmask layer disposed over the first hardmask layer, the second hardmask layer adapted to be removed during formation of interconnect structures in the semiconductor intermediate.
The intermediate semiconductor device may further include a third hardmask layer disposed over the second hardmask layer, the third hardmask layer adapted to be removed during formation of interconnect structures in the semiconductor intermediate. Op

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