Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-05
2004-04-27
Wong, Don (Department: 2821)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C438S585000, C438S591000
Reexamination Certificate
active
06727134
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a gate dielectric layer comprised with silicon nitride, for complimentary metal oxide semiconductor (CMOS), devices.
(2) Description of Prior Art
The emergence of micro-miniaturization has allowed metal oxide semiconductor field effect transistor (MOSFET), or complimentary metal oxide semiconductor (CMOS), devices featuring sub-0.10 um channel lengths to be realized. Advances in specific semiconductor fabrication disciplines, such as photolithography and dry etching, have in part been responsible for attainment of the devices comprised with sub-micron features. The use of micro-miniaturization also necessitates the use of ultra-thin gate dielectric layers, wherein the thinner gate dielectric layers have to withstand device operating conditions experienced by thicker gate dielectric counterparts. The use of a composite dielectric stack such as a silicon nitride-silicon oxide layer offers dielectric strength comparable to thicker silicon oxide gate dielectric counterparts and thus is a desirable candidate for use in sub-0.10 um MOSFET devices, however the process sequence used to form the silicon nitride-silicon oxide stack can be cumbersome, costly and difficult to control the ultra-thin components of the stack. Generally a four step process sequence, featuring growth of an underlying silicon oxide layer, deposition of a thin silicon nitride layer, a high temperature anneal, and a high temperature reoxidation, is used for attainment of the silicon nitride-silicon oxide gate stack. This process sequence can result in thicker than desired stack components via the use of the required higher deposition, anneal, and reoxidation temperatures.
The present invention will describe a simplified process sequence in which a thin nitride-oxide gate dielectric stack is formed, featuring low temperature processing, and featuring improved thickness uniformity, yield and reliability, when compared to counterpart gate dielectric stacks prepared without the use of this invention. Prior art such as Bloom et al, in U.S. Pat. No. 6,228,779 B1, Chew et al, in U.S. Pat. No. 6,225,169 B1, Raaijamakers et al, in U.S. Pat. No. 6,348,420 B1, and Yu et al, in U.S. Pat. No. 6,362,085 B1, describe methods of forming composite dielectric stacks, however none of the prior art describe the novel process sequence detailed in the present invention.
SUMMARY OF THE INVENTION
It is an object of this invention to form a nitride-oxide stack for use as a gate dielectric in complimentary metal oxide semiconductor (CMOS), devices.
It is another object of this invention to initially form the nitride component of the nitride-oxide stack on a semiconductor substrate, via a plasma nitridization procedure which provides excellent nitride thickness uniformity and controllability, independent of plasma nitridization time.
It is still another object of this invention to employ a subsequent plasma oxidation procedure to grow the underlying oxide component of the nitride-oxide stack on the surface of an underlying semiconductor substrate, with the same plasma oxidation procedure removing bulk traps in the overlying nitride component.
In accordance with the present invention a method of forming a nitride-oxide stack for use as a gate dielectric layer featuring a plasma nitridization procedure to uniformly and controllably form the nitride component of the dielectric stack on a semiconductor substrate, and featuring a subsequent plasma oxidation procedure used to form the underlying oxide component of the dielectric stack on the surface of the semiconductor substrate while repairing bulk traps in the nitride component, is described. A plasma nitridization procedure is performed to grow a uniform, thin silicon nitride layer on the surface of a semiconductor substrate using a low growth temperature which allows the growth of the nitride component of the nitride-oxide stack to be self-limiting in regards to thickness. A plasma oxidation procedure is next in situ performed at a low temperature, removing bulk traps in the silicon nitride layer, while growing the thin silicon oxide component of the nitride-oxide stack on the surface of the semiconductor substrate, underlying the nitride component. The plasma oxidation procedure results in a top portion of the silicon nitride layer being converted to a silicon oxynitride layer. The removal of bulk traps result in a reliable nitride-oxide stack, while the low thermal budget of the plasma steps, and the in-situ plasma procedures result in wide process windows as well as process cost reductions.
REFERENCES:
patent: 6033998 (2000-03-01), Aronowitz et al.
patent: 6087229 (2000-07-01), Aronowitz et al.
patent: 6225169 (2001-05-01), Chew et al.
patent: 6228779 (2001-05-01), Bloom et al.
patent: 6348420 (2002-02-01), Raaijmakers et al.
patent: 6362085 (2002-03-01), Yu et al.
patent: 6436771 (2002-08-01), Jang et al.
Chen Chi-Chun
Chen Shih-Chang
Lee Tze-Liang
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Tran Thuy Vinh
Wong Don
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