Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-08-03
2004-07-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S738000, C365S201000
Reexamination Certificate
active
06760871
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to testing of integrated circuit devices and, in particular, to testing packet-based semiconductor memories and the devices themselves.
BACKGROUND OF THE INVENTION
As the complexity of semiconductor integrated circuits continues to increase, difficulties begin to arise in the use of generalized test equipment to ensure the desired operability of each device. The increasing complexity of these devices is driven largely by the need to increase speed and bandwidth and, as such, the architecture of these devices changes to achieve this result. These changes in device architecture, in many cases, make the utilization of existing test equipment difficult, if not impossible. Purchasing new test equipment is often economically undesirable, particularly if only a segment of a production line utilizes these device architectures.
The generalized test equipment used to test semiconductor integrated circuits may vary between manufacturer and intended use, but in general, the test equipment is used to monitor processes, test board and box level assemblies, and may be used to test the functionality of an integrated circuit.
One type of test equipment that is of particular interest in the case of manufacturing memory devices is referred to as a “memory tester.” Hereinafter, the terms “memory tester” and “tester” will be used interchangeably. Memory testers allow for the functional testing of integrated memory circuits to identify defects at the time of test. Identification of a defective device gives the manufacturer the options of reworking, repairing, or possibly scrapping the device. Because of the cost added at each step of the manufacturing process, the earlier a defect can be discovered, the more cost efficient the manufacturing process will be.
Functionally testing integrated memory circuits typically involves the development of a logical model of the device to be tested. The model defines input pins for the application of stimuli to the device under test (DUT) and output pins for observation of the response from the DUT. Logical models are typically developed with the requirements of the intended tester in mind. With an accurate model, a measured response from a DUT can be compared against the anticipated model response, and if it does not match, then a faulty device has been detected.
In a typical tester, an algorithmic pattern generator (APG) is provided as a resource for stimuli of the input pins of a DUT. The APG typically provides a first X address generator and a second Y address generator. To illustrate the operation of an APG, imagine writing zeros into every address of a DUT. In this case, the data generator would generate a continuous “0.” The X address generator would run from “0” to a predefined end address, whereas the Y address generator would maintain its initial value. Once the X address generator reaches its end address, it would be reset to “0,” the Y address generator would be increased by one, and the X address generator would again run from “0” to its end address. This process would continue until all cells of the memory under test contained a “0.”
The controller of such an APG typically includes a programmable vector memory for storing test patterns. Vector memory is typically limited in size. If a sufficiently large number of test patterns are necessary to test a given device, it may require loading more than one set of test patterns in vector memory to complete the test. Thus, it is advantageous to use an APG where possible to preserve available vector memory and allow for more efficient operation.
A packet-based semiconductor memory operates on more than one word of information in a given cycle. The packet information could be data, address, command or any other type of data which the device is capable of receiving or outputting. The number of words in a given packet cycle is determined by the particular device architecture. The term “data packets” and “packets” are used interchangeably herein to include data, address and command information.
Because many tester APGs have only X and Y address generators, it is difficult to generate more than two bits of APG data as input stimuli to a DUT. The same problem would arise for an APG with N address generators if one was attempting to generate more than N bits of APG data. Herein lies the problem with testing integrated memory circuits which require packet-based information. With packet-based devices, there may be a need for more than two bits of APG data per input pin as stimuli. This may require the use of vector memory to supply the additional information bits.
To illustrate the problem, consider, for example, the draft specification for a 4 Megabit×18 I/O Synchronous-Link Dynamic Random Access Memory (SLDRAM). The draft specification for this packet-based semiconductor memory is titled
Draft/Advance, SLDRAM Inc., SLD
4
M
18
DR
400, 4
MEG×
18
SLDRAM
, Rev. Feb. 12, 1998.
FIG. 1
is a table reproducing the information in a Read, Write or Row Operation Request Packet, as defined in the above-referenced draft specification, page 7, which comprises four 10-bit words, WORD
0
, WORD
1
, WORD
2
, and WORD
3
. As depicted, the first row of data under the column heading represents prior data in a packet stream, which are not of concern, hence the “don't care” or “x” value placed within each bit location. Each column of data represents an input pin on the SLDRAM device, including the Flag bit. The Command Address bits, CA
0
-CA
9
, define the 10-bit command words. The beginning of a packet is indicated by the Flag bit being in a logical true. The Flag bit logical true also indicates that the first word in a packet, WORD
0
, is present on the CA
0
-CA
9
bits.
The data within each of the four command words, WORD
0
-
3
, are latched with timing signals not shown in FIG.
1
. WORD
0
contains the nine identification bits, ID
0
-ID
8
, used to identify a particular SLDRAM in an array of such memory devices, as well as CMD
5
, which is one of six command code bits. WORD
1
contains CMD
0
-
4
, BNK
0
-
2
, and ROW
8
-
9
. The command bits CMD
0
-
5
are used to instruct the SLDRAM to perform a particular memory operation. For example, where all six of the CMD
0
-
5
bits are zero, the command is: Page Access, Burst of 4, Read Access, Leave Row Open, Drive DCLK
0
. The bank address bits BNK
0
-
2
are used to select one of eight memory banks, where each memory bank is 1024 rows×128 columns×72 bits in size. WORD
2
contains eight of the row address bits, ROW
0
-
7
, and two unused bits. WORD
3
contains seven column address bits, COL
0
-
6
, and three unused bits.
The address bits, bank, row and column are particularly suitable for algorithmic pattern generation because it is frequently the case that one wants to sequence through the addresses when performing a read or write operation. In contrast, the command code bits CMD
0
-
5
are accessed in a more or less random order, so vector memory is more appropriate and convenient as a source of test patterns. In
FIG. 1
, this test pattern source preference has been indicated by the abbreviations “vm” for vector memory and “apg” for algorithmic pattern generator.
Ideally, the bank, row and column addresses would each be assigned one of the address generators in the APG. However, as noted above, conventional APGs typically have only two address generators, X and Y. To illustrate the problem, refer to
FIG. 1
, column CA
3
, which represents command address pin
3
. For pin CA
3
, the tester must provide three pieces of algorithmic data, BNK
1
, ROW
1
, and COL
3
, in addition to ID
2
, which is sourced from vector memory. Furthermore, WORDs
1
-
3
contain combinations of data from vector memory and an APG.
In most cases, it is possible to create a description of a combination of required vectors and APG bits to accommodate each of the cycles described in a typical packet. This approach, however, requires much additional work to format pins appropriately and may consume additional tester res
De'cady Albert
Lamarre Guy
TraskBritt
LandOfFree
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