Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-07-10
2004-07-13
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S297000, C438S298000
Reexamination Certificate
active
06762103
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming an isolation film in a semiconductor device using a shallow trench, and more particularly, to a method of forming an isolation film in semiconductor devices by which the depths of trenches in a memory cell region and a peripheral circuit region are differently formed.
2. Background of the Related Art
As the degree of integration in semiconductor memory devices is increased, the size of the memory cell is reduced. Therefore, in implementing the flash memory device recently, an isolation film using a shallow trench is employed in order to secure the ratio of the memory cell per wafer.
In the flash memory device having electrical programming and erasing functions, a high voltage is applied to a control gate of the memory cell upon programming and erasing. Due to this, many transistors for high voltage are used in the flash memory devices.
Upon formation of the isolation film conventionally, however, trenches having the same depths are formed in the memory cell region and the peripheral circuit region. Therefore, many electrical problems occur due to application of the high voltage.
In case of the DRAM, a bias voltage of the maximum 5V is applied. In case of the flash memory, however, a bias voltage of 18~24V is applied. If the depth of the trench in the peripheral circuit region is made shallow, a punch through occurs in the well of the NMOS transistor and the PMOS transistor. Further, if the depth of the trench in the memory cell region is made deep, the sheet resistance in the common source is increased, so that the operating speed is lowered during the programming, erasing and reading operation in a block unit. This reduction in the operating speed causes a problem due to difference between the bias voltages for programming, erasing and reading.
It is thus required that the depths of the trenches in the memory cell region and the peripheral circuit region be differently formed. A conventional method includes one by which trenches having difference depths are formed in the memory cell region and the peripheral circuit region, respectively, using different mask patterns, or one by which trenches having the same depths are formed in the memory cell region and the peripheral circuit region, respectively, and the depth of the trench in the peripheral circuit region is increased by means of etch process using a given mask.
However, the above methods have the following disadvantages. First, it is difficult to form the trenches having the same depths on the entire wafer in view of etch process. Second, residues are created due to difference in the etch depth. Third, the leakage current occurs due to damage of the substrate depending on physical etch, in particular etch damage of the bottom of the trench, and a punch through problem thus occurs in the device for high voltage. Fourth, the productivity is lowered due to addition of etch process for increasing the depth of the trench in the peripheral circuit region.
SUMMARY OF THE INVENTION
Accordingly, the present invention is contrived to substantially obviate one or more problems due to limitations and disadvantages of the related art, and an object of the present invention is to provide a method of forming an isolation film in semiconductor devices by which trenches are formed in silicon substrates of a memory cell region and a peripheral circuit region, an inert ion is implanted into the surface of the trench in the peripheral circuit region to form an amorphous layer, and an oxidization process is then implemented to grow a thick oxide film by means of excessive oxidization at the amorphous layer.
In a preferred embodiment, a method of forming an isolation film in semiconductor devices according to the present invention is characterized in that it comprises the steps of forming a mask pattern on a silicon substrate in a memory cell region and a peripheral circuit region and then etching an exposed portion of the silicon substrate by a given depth to form a shallow trench, implanting an inert ion into the surface of the trench in the peripheral circuit region, implementing an oxidization process so that an oxide film is grown on the surfaces of the trenches in the memory cell region and the peripheral circuit region, wherein the depth of the trench in the peripheral circuit region is increased due to excessive oxidization at the portion in which the ion is implanted, and forming an oxide film on the entire structure so that the trench is buried and planarizing the surface of the oxide film.
The inert ion is entire silicon (Si) or argon (Ar). The oxidization process is implemented at a temperature of 800~1100° C. to a target thickness of 30~150 Å.
The method further comprises the step of after the inert ion is implanted, performing a rapid thermal oxidization process using a spike annealing process so that an anti-diffusion layer is formed at the bottom of the trench. The spike annealing process is implemented at a temperature of 850~1100° C. and the ramp-up ratio is controlled to be 100~250° C./sec.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In another aspect of the present invention, it is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6265292 (2001-07-01), Parat et al.
patent: 6323106 (2001-11-01), Huang et al.
patent: 6504219 (2003-01-01), Puchner et al.
Dong Cha Deok
Kwak Noh Yeal
Park Sang Wook
Hynix / Semiconductor Inc.
Le Dung A.
Marshall & Gerstein & Borun LLP
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