Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-01-04
2004-07-06
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S705000, C438S775000
Reexamination Certificate
active
06759315
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to the field of transistor gate conductor structures in semiconductor devices. More specifically, the invention relates to a method for forming a trimmed gate in a transistor and the apparatus formed thereby.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced. The push for ever increasing device densities is particularly strong in complimentary metal-oxide semiconductor (CMOS) technologies, such as in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.)
One feature that increases device density is a “trimmed” gate conductor. In general, it is desirable to make gate conductors smaller in semiconductor devices so the associated FETs are faster and operate at lower power. Typically, lithographic methods are used to define gate conductors and then etch processes trim the lithographically formed structure to create sub-lithographic dimensions. However, etch processes are limited in the magnitude of material that can be trimmed from a gate conductor while still maintaining the proper scale of the device. That is, as more of the gate conductor is trimmed by etching, the risk of producing a distorted or defective gate conductor increase. Since sidewall spacers, contacts to diffusion areas, contacts to gates, etc. are typically formed after trimming, distorted gates can lead to misalignment of device components and failure of the device. Accordingly, additional methods are needed that may be combined with current methods or used alone to further trim gate conductors or trim gate conductors by a different technique than presently available.
Another problem with the current fabrication of FETs is that methods for device compensation are in need of improvement. Device compensation is where the relative size (i.e., the gate width to length ratio) of some devices is changed. There are several reasons why device compensation might be required. For example, the speed of CMOS FETs is critically dependant on the width to length ratio of a gate on a given device. In many cases, circuit design requires individual compensation of n-channel and p-channel performance to achieve proper timing between devices. This requires the ability to selectively compensate the width to length ratio of n-channel and p-channel devices. For example, the timing of logic circuitry critically depends on accurate speed control on n-channel as well as p-channel devices, and this may require shortening the length of all n-channel devices by one amount and shortening the length of all p-channel devices by another amount. Thus, as CMOS processes mature, the ability to selectively adjust the physical gate length of n-channel and p-channel devices to compensate for process and device-physics induced speed differences is needed.
Therefore, there existed a need to provide an improved method for trimming gate conductors and an improved method of selective device compensation.
DISCLOSURE OF INVENTION
According to the present invention, a method is provided for forming a trimmed gate in a transistor comprising the steps of forming a polysilicon portion of a gate conductor on a substrate having a semiconductor portion and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. By way of example, the trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. Also according to the present invention, a transistor is provided comprising a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.
REFERENCES:
patent: 4298629 (1981-11-01), Nozaki et al.
patent: 4434189 (1984-02-01), Zaplatynsky
patent: 4592933 (1986-06-01), Meyerson et al.
patent: 4672169 (1987-06-01), Chambers
patent: 4715937 (1987-12-01), Moslehi et al.
patent: 4900396 (1990-02-01), Hayashi et al.
patent: 5319231 (1994-06-01), Yamazaki et al.
patent: 5330936 (1994-07-01), Ishitani
patent: 5348900 (1994-09-01), Ayukawa et al.
patent: 5364804 (1994-11-01), Ho et al.
patent: 5376578 (1994-12-01), Hsu et al.
patent: 5397722 (1995-03-01), Bashir et al.
patent: 5593783 (1997-01-01), Miller
patent: 5620912 (1997-04-01), Hwang et al.
patent: 5648284 (1997-07-01), Kusunoki et al.
patent: 5668065 (1997-09-01), Lin
patent: 5720642 (1998-02-01), Hattori
patent: 5780330 (1998-07-01), Choi
patent: 5899742 (1999-05-01), Sun
patent: 5966606 (1999-10-01), Ono
patent: 6057220 (2000-05-01), Ajmera et al.
patent: 6127267 (2000-10-01), Matsuara et al.
patent: 6200868 (2001-03-01), Mase et al.
patent: 6204130 (2001-03-01), Gardner et al.
patent: 6214684 (2001-04-01), Shoji
patent: 6228717 (2001-05-01), Hazama et al.
patent: 6251763 (2001-06-01), Inumiya et al.
patent: 360068655 (1985-04-01), None
patent: 411274143 (1999-10-01), None
Stanasolovich, et al. “Method for Reducing the Diffusion Contact Borders”, IBM Technical Disclosure Bulletin, vol. 32, No. 4A, Sep. 1989, pp. 344-345.
Weiner et al. “Self Aligned Silicide Formation Using Gas Immersion Laser Annealing (GILA)”, Ultratech Stepper technical brief, Mar. 3, 1997.
Weiner et al., “Ultrashallow Junction Formation Using Projection Gas Immersion laser Doping (PGILD)”, Verdant Technologies technical brief, Aug. 20, 1997.
Derwent World Patent Index “Japanese Patent 8148680 Abstract”, Jun. 7, 1996.
Jasinki et al. 27341 “Photochemical Deposition of Graded Silicon Nitride”, Research Disclosure, Jan. 1987, No. 273.
Jasinki et al. 27343 “Photochemical Deposition of Silicon Nitride”, Research Disclosure, Jan. 1987, No. 273.
Mihailescu et al. “Direct nitridation of a silicon surface by multipulse excimer laser irradiation in a nitrogen-containing ambient gas”, Journal of Applied Physics 70, Aug. 15, 1991, pp 2123-2131.
Mihailescu et al. “Synthesis and deposition of silicon nitride films by laser reactive ablation of silicon in low pressure ammonia: A parametric study”, Journal of Vacuum Science Technology 14, Jul./Aug. 1996, pp 1986-1994.
Furukawa Toshiharu
Hakey Mark C.
Holmes Steven J.
Horak David V.
Rabidoux Paul A.
Fourson George
Garcia Joannie Adelle
Sabo William D.
Schmeiser Olsen & Watts
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