Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-04-15
2004-05-18
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S230000, C438S253000, C438S639000
Reexamination Certificate
active
06737314
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device such as a MOS transistor which is to be used for a DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
The DRAM (Dynamic Random Access Memory) is constituted by a memory cell array to act as a storage region for storing memory information and a peripheral circuit portion for causing the memory cell array to perform a predetermined input/output operation. The memory cell array is provided with a plurality of memory cells corresponding to minimum storage units. The memory cell in the DRAM is basically constituted by one capacitor and one MOS (Metal Oxide Semiconductor) transistor connected to the capacitor. In the operation, it is decided whether predetermined electric charges are stored in the capacitor or not. The decision is caused to correspond to data “0” and “1”, thereby storing information.
FIG. 34
is a typical equivalent circuit of the memory cell of the DRAM. As shown in
FIG. 34
, a memory cell
200
comprises a capacitor
201
and a cell transistor
202
. One electrode of source/drain electrodes of the cell transistor
202
is connected to one electrode of the capacitor
201
, and a bit line
203
is connected to the other electrode of the cell transistor
202
. Moreover, a gate-electrode of the cell transistor
202
is connected to a word line
204
and the bit line
203
is connected to a sense amplifier
205
.
The expression of “source/drain” is used for the electrode to function as a source for supplying carriers and to fulfill the function of taking out (draining) the carriers by reading or writing information.
FIG. 35
is a sectional view showing a structure of a conventional memory cell. In
FIG. 35
, a partially hidden part is shown in a broken line. As shown in
FIG. 35
, an STI (Shallow Trench Isolation)
102
made of an isolation oxide film or the like is formed on a p-type semiconductor substrate
101
, thereby electrically insulating elements.
An n-type MOS transistor comprises a gate insulating film
103
, a gate-electrode
104
, n-type source/drain regions
105
and
106
, a sidewall
107
and an insulating film
108
. The gate-electrode
104
is also caused to function as the word line
204
.
The source/drain regions
105
and
106
are selectively formed on a surface of the semiconductor substrate
101
with the gate-electrode
104
interposed therebetween. The sidewall
107
is an insulating film for covering the gate-electrode
104
, and the insulating film
108
is formed under the sidewall
107
adjacent to the gate insulating film
103
.
A polysilicon pad
110
a
has a bottom face connected to the source/drain region
106
and a top face connected to a storage node
111
which will be described below. On the other hand, a polysilicon pad
110
b
has a bottom face connected to the source/drain region
105
and a top face connected to a bit line
113
shown in a broken line over a region which is not shown in FIG.
35
.
An interlayer dielectric film
112
is formed over the whole surface of the semiconductor substrate
101
including the MOS transistor and the polysilicon pads
110
a
and
110
b
, and a silicon nitride film
114
is formed above the interlayer dielectric film
112
.
A memory cell capacitor
118
is formed in a region on the silicon nitride film
114
. The memory cell capacitor
118
is constituted by a lower electrode
115
, rough surface polysilicon
120
, a capacitor dielectric film
116
and a cell plate
117
. The lower electrode
115
is made of a material such as amorphous silicon doped with phosphorus or doped polysilicon. The capacitor dielectric film
116
comprises a silicon oxide film, a silicon nitride film, a high dielectric film and the like. The cell plate
117
is made of polysilicon containing n-type impurities. The lower electrode
115
of the memory cell capacitor
118
is electrically connected to the polysilicon pad
110
a
through the storage node
111
formed penetrating the interlayer dielectric film
112
.
Electric charges stored as memory information in the memory cell capacitor
118
are gradually discharged by a leakage current in an n-p junction portion of the source/drain regions
105
and
106
and the semiconductor substrate
101
, the capacitor dielectric film
116
or the like. Therefore, it is necessary to perform an operation for timely injecting electric charges in order to continuously hold the storage in a DRAM. This operation is referred to as refresh.
The refresh operation will briefly be described below. First of all, the contents of information written to the capacitor
201
are read and decided by the sense amplifier
205
. Then, if it is decided based on the decided contents of the information that electric charges are injected into the capacitor
201
, electric charges are newly supplied. If it is decided based on the decided contents of the information that the electric charges are not injected, a writing operation is performed such that the electric charges in the capacitor
201
are eliminated.
The refresh operation is performed by applying a voltage to the selected gate-electrode
104
and source/drain region
105
to read and write the information stored in the memory cell capacitor as described above.
In a conventional semiconductor memory, however, a leakage current has been generated on a storage node and an n-p junction portion of a source/drain region of a MOS transistor and a semiconductor substrate to eliminate information in addition to the elimination of the information caused by the reading operation. In order to prevent the information from being eliminated by the leakage current, the refresh operation should be performed for information stored in all memory cells in a comparatively short cycle of about 1 msec to several hundreds msecs. Thus, there has been a problem in that power consumption of the semiconductor memory is increased by frequently performing the refresh operation.
Moreover, there has been a problem in that a time interval for refresh (a pause-refresh time) becomes short because the information stored in the memory cell cannot be read out during the refresh operation. If the pause-refresh time is short, a data utilization ratio for the operation is reduced.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device which can obtain a MOS transistor having a reduction in a leakage current without unnecessarily damaging an integration degree.
A first aspect of the present invention is directed to a method for manufacturing a semiconductor device in which first and second MOS transistors of a second conductivity type are formed in first and second regions provided in an upper layer portion of a semiconductor substrate of a first conductivity type, respectively, comprising the steps of (a) forming a first source/drain region pair of a second conductivity type, a channel region of the first conductivity type which is positioned in the first source/drain region pair, and a gate-electrode region positioned on the channel region in the first and second regions, respectively, (b) forming a first sidewall on side-faces of the gate-electrode region of each of the first and second regions, (c) forming an interlayer dielectric film over a whole surface and forming a trench in only the first region through the interlayer dielectric film such that a side-face of the first sidewall is exposed, and (d) forming an insulating film for forming a second sidewall over a whole surface including the side-face of the first sidewall in the trench, and then removing the insulating film for forming the second sidewall in portions other than an inside of the trench, thereby forming the second sidewall on the side-face of the first sidewall, wherein the first MOS transistor is constituted by the first and second sidewalls, the first source/drain region pair, the channel region and the gate-electrode region in the
Cao Phat X.
Doan Theresa T.
Renesas Technology Corp.
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