Series memory architecture

Details Series memory architecture Series memory architecture

2002-09-19

2004-04-13

Mai, Son L. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S298000, C257S300000, C257S303000, C438S003000, C438S250000, C438S393000

Reexamination Certificate

active

06720598

ABSTRACT:

BACKGROUND OF INVENTION
Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semiconductor memory devices. The ferroelectric material is located between two electrodes to form a ferroelectric capacitor for storage of information. Ferroelectric capacitor uses the hysteresis polarization characteristic of the ferroelectric material for storing information. The logic value stored in a ferroelectric memory cell depends on the polarization direction of the ferroelectric capacitor. To change the polarization direction of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. The polarization of the capacitor depends on the polarity of the voltage applied. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
Referring to
FIG. 1
, a group
102
of memory cells
105
is shown. The memory cells, each with a transistor
130
coupled to a capacitor
140
in parallel, are coupled in series. Such series memory architectures are described in, for example, Takashima et al., “High Density Chain Ferroelectric Random Access Memory (chain FRAM)”, IEEE Jrnl. of Solid State Circuits, vol.33, pp.787-792, May 1998, which is herein incorporated by reference for all purposes. The gates of the cell transistors can be gate conductors which are coupled to or serve as wordlines. A selection transistor
138
is provided to selectively couple one end
109
of the group to a bitline
150
. A plateline
180
is coupled to the other end
108
of the group. Numerous groups are interconnected via wordlines to form a memory block. Sense amplifiers are coupled to the bitlines to facilitate access to the memory cells.
FIG. 2
shows a cross-section of a conventional memory group
202
. The transistors
230
of the memory cells
205
are formed on a substrate
210
. Adjacent cell transistors share a common diffusion region. The capacitors
240
of the memory group are arranged in pairs. The capacitors of a capacitor pair share a common bottom electrode
241
. The bottom electrodes are coupled to the cell transistors via active area bottom electrode (AABE) plugs
285
. The top electrode
242
of a capacitor from a capacitor pair is coupled to the top electrode of a capacitor from an adjacent capacitor pair and cell transistors. The top capacitor electrodes are coupled to the cell transistors via active area top electrode (AATE) plugs
286
. Between the electrodes is a ferroelectric layer
243
. A barrier layer
263
, such as iridium oxide, is located between the electrode and the AABE plug. At a first end
209
of the group is a selection transistor (not shown) having one diffusion region coupled to a bitline. The other diffusion region is a common diffusion region with the cell transistor on the end of the group. A plateline is coupled to a second end
208
of the group.
The series architecture theoretically enables a 4F
2
cell size, where F is the feature size. However, conventional series architectures require a sufficient capacitance to produce a sufficient read signal for sensing. To produce the necessary capacitance, a capacitor with relatively large surface area is needed. This undesirably increases the cell size to greater than 4F
2
.
From the foregoing discussion, it is desirable to provide a memory group which avoids the disadvantages of conventional series memory architectures.
SUMMARY OF INVENTION
The invention relates generally to ICs. More particularly, the invention relates to ICs with a plurality of memory cells having a series architecture. The memory cells of the group are arranged into pairs of memory cells. A memory cell pair comprises a first memory cell having a first transistor with a gate and first and second diffusion regions and a first capacitor with first and second plates separated by a first capacitor dielectric and a second memory cell having a transistor with a gate and first and second diffusion regions and a second capacitor with first and second plates separated by a second capacitor dielectric. In one embodiment, the second diffusion regions of the first and second transistors of the memory cell pair, is a common second diffusion region. The first and second capacitors are arranged in a stack in which the second plates of the capacitors form a common second plate. The first plate of the first capacitor is coupled to the first diffusion region of the first transistor, the first plate of the second capacitor is coupled to the first diffusion region of the second transistor, and the common second plate is coupled to the common second diffusion region. In one embodiment, the memory cells are ferroelectric memory cells. By providing a memory cell pair of a series group in which the capacitors are stacked advantageously allows larger capacitors for the memory cells without increasing cell size, for example, beyond 4F
2
.


REFERENCES:
patent: 5903492 (1999-05-01), Takashima
patent: 2002/0075736 (2002-06-01), Kumura et al.

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