Semiconductor integrated circuit with a scan path circuit

Details Semiconductor integrated circuit with a scan path circuit Semiconductor integrated circuit with a scan path circuit

2000-06-07

2004-01-13

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06678846

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a scan path circuit and a device using the same. More specifically, it relates to an electric system that is designed to facilitate a scan path test with respect to a logic circuit.
2. Description of the Prior Art
FIG. 21
is circuit diagram showing a semiconductor integrated circuit with a scan path circuit as one example of a conventional electric system. In
FIG. 21
, the reference numeral
1
′ designates a scan path circuit;
5
′ designates a logic circuit to be tested;
11
′-
1
to
11
′-n each designate a scan register circuit (n=natural number);
13
designates a flip-flop circuit;
17
designates a multiplexer circuit; I
11
designates an inverter circuit; and N
21
, N
22
each designate a node.
Such a conventional semiconductor integrated circuit is typically composed of the logic circuit
5
′ and scan path circuit
1
′. The scan path circuit
1
′ is constituted by connecting the plurality of scan register circuits
11
′-
1
to
11
′-n in series, each of which has terminals D
1
, SI, SM, T on the input side and terminals QC and Q on the output side. As shown in
FIG. 21
, the scan register circuits
11
′-
1
to
11
′-n each have the flip-flop circuit
13
, multiplexer circuit
17
, and inverter circuit I
11
.
Here, the flip-flop circuit
13
has a data input terminal d and a clock terminal t on the input side, and a non-inversion data output terminal q and an inversion data output terminal qc on the output side. The circuit
13
takes in data at the data input terminal d in synchronization with a clock signal through the terminal T of one corresponding scan register circuit, and outputs the data from the non-inversion data output terminal q to the logic circuit
5
′ and further outputs the data from the inversion data output terminal qc to the logic circuit
5
′ and a scan register circuit at the next stage through the node N
21
and terminal Q.
The multiplexer circuit
17
is composed of two OR circuits and one NAND circuit, and selects data at the terminal DI or SI to transfer the data at the terminal d of the flip-flop circuit
13
as a memory circuit. This selection is carried out by a SM signal or shift mode signal through the terminal SM: the terminal SI is selected when the SM signal is “1”, while the terminal DI is selected when the SM signal is “0”.
Here, the scan path circuit
1
′ operates as a serial shift resister in which the terminals SIP and SOP are set at the input and output, respectively when the SM signal is “1”, while it operates as a register that takes in from the terminal DI and then outputs the data form the terminals Q and QC.
FIG. 22
is a layout schematic of a semiconductor integrated circuit device employing the semiconductor integrated circuit as shown in FIG.
21
. In
FIG. 22
, the reference numeral
21
′ designates a semiconductor integrated circuit device; a
1
-an, b
1
-bn, b
11
-bn
1
, and b
12
-bn
2
each designate a wire; and N
1
-Nn each designate a node, and marks which are the same as the above are identified by the same or corresponding parts and these explanation will be omitted. The wires a
1
-an connects the terminals QC of the scan register circuits
11
′-
1
to
11
′-n to the logic circuit
5
′, respectively, while the wires b
1
-bn are connected to the terminals Q and branch to the wires b
11
-bn
1
and wires b
12
-bn
2
at the node N
1
-Nn, respectively, and serially connected to the logic circuit
5
′ and the scan register circuit at the next stage (e.g., in the case of the scan register circuit
11
′-
1
, the next stage is the scan register circuit
11
′-
2
).
As shown in
FIGS. 21 and 22
, in the semiconductor integrated circuit with a scan path circuit and the device employing this circuit, a test of the electronic system is carried out by a so-called scan test.
The operation of the scan test will be next described.
In a step ST
1
, the shift mode signal is set to SM=“1”, and test data are serially shifted in from the terminal SIP to the scan path circuit
1
′ while a plurality of clock pulses are given to the terminal T of each scan register circuit that is connected to the terminal t of the corresponding flip-flop circuit
13
. Subsequently, in a step ST
2
, it is set to SM=“0”, and by supplying one clock pulse to the terminal T, test results of the logic circuit
5
′ to the test data are taken in the scan path circuit
1
′. Then, in a step ST
3
, it is set to SM=“1” again, and the test results in the scan path circuit
1
′ are serially shifted out from the terminal SOP while a plurality of clock pulses are given to the terminal T. Further, in a step ST
4
, the above steps ST
1
to ST
3
are repeated. Note that in the step ST
3
, the operation of the step ST
1
also may be simultaneously implemented.
Next,
FIG. 23
is a circuit diagram showing one example of a conventional CMOS scan path register circuit, which may be constituted in a CMOS semiconductor circuit device. It should be noted that a connection drawn by a dotted line may be omitted. In
FIG. 23
, the reference numerals N
1
-N
14
, N
17
, N
30
, N
31
each designate a NMos transistor; and P
1
-P
14
, P
17
, P
30
, P
31
each designate a PMOS transistor. The NMOS transistors N
1
-N
3
, N
30
and the PMOS transistors P
1
-P
3
, P
30
constitute a multiplexer circuit
17
.
As shown in
FIGS. 21 and 23
, in many cases, the multiplexer circuit employed in the conventional CMOS scan register circuit is often constituted by employing an OR-NAND compound gate integrated with two OR circuits and one NAND circuit. Here, the compound gate is a function block that is constituted by a combination of a plurality of simple gates such as AND, OR, and inverter. Since this kind of compound gate is commonly optimized when prepared by a vendor, the number of components may be minimized as compared to a case that performs the same function by only simple gates, thereby providing excellent characteristics in consumption power and operating speed.
There is JP-A 06/160479(1994) as a disclosure of a semiconductor integrated circuit prepared with a transfer gate and a latch between an output QC of a flip-flop circuit and a multiplexer circuit at the next stage. In addition, there is JP-A 05/157807(1993) as a memory circuit provided with a transfer gate prepared between an output QC and a multiplexer at the next stage.
Thus, since a scan register circuit is typically provided by a semiconductor or cell library vendor as a simple cell within a cell library in a hierarchy design method, it is common that a flip-flop circuit and a multiplexer circuit in the scan register is fixedly connected with each other.
Since the semiconductor integrated circuit with a scan path circuit and the device using this circuit in the prior art are constituted as, described above, serial wires (Q to SI) for serial shift registers through the nodes N
1
-Nn are connected to the respective output terminals Q of the scan register circuits
11
′-
1
to
11
′-n constituting the scan path circuit
1
′. Since the serial wires become a capacitance element, there arise problems such as delay increase at the output Q and increased consumption power.
SUMMARY OF THE INVENTION
The present invention has been implemented to solve the foregoing problems. It is therefore an object to provide a semiconductor integrated circuit and a device with this circuit which prevent delay of an output Q and reduce consumption electric power.
According to a first aspect of the present invention, there is a provided a semiconductor integrated circuit comprising: a scan path circuit being constituted by serially connecting a plurality of scan register circuits, each of which is constituted by an OR-NAND compound gate circuit, a flip-flop circuit, and an OR circuit; and a logic circuit to be tested by use of the scan pat

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