Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-06
2004-05-18
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S413000, C257S506000
Reexamination Certificate
active
06737315
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device allowing improvement in yield.
2. Description of the Background Art
In a semiconductor integrated circuit, when diverse elements should operate in a totally independent manner without electrical interaction thereamong, it is required to provide an element isolation structure having an element isolation region.
A well-known technique of forming an element isolation region is trench isolation, on which several improvements have been suggested. According to the trench isolation technique, a trench is defined in a substrate and then filled with an insulating material. Trench isolation offers little probability of bird's beak and therefore, is recognized as one of the essential techniques of element isolation allowing shrinkage of a semiconductor integrated circuit.
A background-art method of manufacturing a semiconductor device will be described with reference to sectional views of
FIGS. 24 through 28
. First, a silicon oxide film
221
P and a silicon nitride film
222
P are stacked in this order on a silicon substrate
10
P. Next, the silicon nitride film
222
P, the silicon oxide film
221
P and the substrate
10
P are sequentially patterned using a photolithography pattern as a mask, to define a trench
11
P in the substrate
10
P (see FIG.
24
). Following this, an inner wall of the trench
11
P is thermally oxidized, to form an inner wall oxide film
223
P. Thereafter a buried oxide film
21
P is entirely deposited by CVD (chemical vapor deposition) (see FIG.
25
).
Next, following CMP (chemical mechanical polishing) using the silicon oxide film
221
P as a stopper, the buried oxide film
21
P is removed in the area defined on the nitride film
222
P. The buried oxide film
21
P is thereafter planarized, to form a buried oxide film
20
P in the trench
11
P (see FIG.
26
).
Thereafter, the silicon nitride film
222
P is removed and the silicon oxide film
221
P is removed using hydrofluoric acid. As a result, trench isolation is completed as illustrated in FIG.
27
.
The next step is ion implantation for forming each well region, channel cut region and channel impurity layer for MOSFETs
201
P and
202
P. The channel impurity layer controls a threshold voltage of each MOSFET. Next, a gate insulating film
206
, a polysilicon film
207
for forming a gate electrode, and a sidewall
208
are provided. Also provided is a source/drain diffusion layer
205
by ion implantation, thus completing a semiconductor device
1
P (see FIG.
28
).
As described, according to the background-art method, the buried oxide film
21
P is entirely deposited by CVD, thus filling the trench
11
P defined in the substrate
10
P with the buried oxide film
21
P.
The trench
11
P will have a higher aspect ratio accompanied by increasing degree of shrinkage. Therefore, the foregoing step of filling the trench
11
P generates a void in the trench
11
P. After CMP and/or removal of the silicon oxide film
221
P using hydrofluoric acid, such void appears on a surface of the silicon oxide film
20
P, forming a minute recess. When an interconnect material for forming an upper interconnect layer is buried in such minute recess and remains therein, a short circuit may be developed in the interconnect layer. That is, generation of void results in the problem involving considerable reduction in yield of an element.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to provide a method of manufacturing a semiconductor device allowing improvement in yield.
According to a first aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (a) through (e). The step (a) forms a first insulating film into a predetermined pattern on a substrate surface of a semiconductor substrate. The step (b) oxidizes an exposed substrate surface after the step (a) to obtain a first oxide film. The step (c) removes at least a part of the first oxide film. The step (d) epitaxially grows a first semiconductor film on the exposed substrate surface after the step (c). The step (e) polishes the first semiconductor film to an extent that an upper surface of the first semiconductor film is not more than an upper surface of the first insulating film in height.
After patterning for forming the first insulating film that provides an element isolation region, the first semiconductor film is epitaxially grown. Therefore, contrary to the background-art method including the step of filling a trench with an oxide film, there will no void to be generated in the element isolation region. As a result, it is allowed to compensate for reduction in yield caused by existence of void. Further, the steps of forming and removing the first oxide film (a so-called sacrificial oxidation process) are performed prior to growth of the first semiconductor film. Therefore, damage to the substrate surface caused in the step of patterning the first insulating film can be eliminated. Further, a clean surface can be obtained. As a result, crystal defects occurring at an interface between the semiconductor substrate and the first semiconductor film are suppressed, thus ensuring high quality of the first semiconductor film. Further, generation of junction leakage current resulting from such crystal defects can be suppressed, thereby allowing improvement in yield. Still further, the first semiconductor film is polished to an extent that the upper surface of the first semiconductor film is not more than the upper surface of the first insulating film in height. In an MISFET, it is therefore allowed to control concentration of electric field at a periphery of the upper surface of the first semiconductor film that is applied from a gate electrode. As a result, an MISFET relieving the problem resulting from such concentration of electric field can be manufactured with high yield.
It is a second object of the present invention to provide the method of manufacturing a semiconductor device allowing steps to be commonly performed in the element forming region and the alignment mark region.
According to a second aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (i) through (l). The step (i) forms an insulating film into a predetermined pattern on a substrate surface of a semiconductor substrate. The semiconductor substrate includes the element forming region and the alignment mark region. The step (j) epitaxially grows a semiconductor film on an exposed substrate surface after the step (i). The step (k) polishes the semiconductor film to an extent that an upper surface of the semiconductor film is not more than an upper surface of the insulating film in height. The step (l) increases a degree of a step height defined on an exposed surface in the alignment mark region to obtain an alignment mark after the step (k).
The steps (i) through (k) are commonly performed in the element forming region and the alignment mark region.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5930620 (1999-07-01), Wristers et al.
patent: 6452246 (2002-09-01), Komori
patent: 6506661 (2003-01-01), Chang et al.
patent: 59-129439 (1984-07-01), None
patent: 09-148426 (1997-06-01), None
Horita Katsuyuki
Kuroi Takashi
Shiozawa Katsuomi
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