Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-08-03
2004-09-07
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000
Reexamination Certificate
active
06789221
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to an integrated circuit comprising an application circuit to be tested and a self-test circuit which is provided for testing the application circuit and comprises an arrangement for generating deterministic test samples which are applied to the application circuit for test purposes, the output signals occurring due to the application circuit in dependence upon the test samples being evaluated by means of a signature register.
BACKGROUND OF THE INVENTION
When manufacturing integrated circuits, there is the general wish to test their operation. Such tests may be performed by external test arrangements. Due to the very high integration density of such circuits, the very high clock rates at which these circuits operate and the required very large number of test vectors, the external tests involve many problems and costs. The high internal clock rates of the integrated circuits are in an unfavorable proportion to the comparably very slow input/output bond pad stages that lead to the exterior. It is therefore desirable to have the possibility of performing a kind of self-test of the integrated circuit. To this end, a self-test circuit is incorporated in the integrated circuit and is used to test the application circuit which is also provided in the integrated circuit. The application circuit represents that circuit which is provided for the actual purpose of use of the integrated circuit.
When such circuits are tested, problems with those components within the circuit occur which produce a so-called “X” during testing, i.e. a signal which cannot be evaluated unambiguously. Such signals are particularly produced by those components that have an analog or a memory behavior. For example, RAMs incorporated in the application circuit may produce arbitrary output signals. Signals produced by such a RAM and propagated by the circuit at its output can no longer be evaluated unambiguously during testing.
To avoid this problem, it is known from the prior art to incorporate special components in the circuit which, during testing, bypass such components or mask the outputs of these components. This has the drawback that additional components must be incorporated in the circuit which, on the one hand, leads to a higher number of components and, on the other hand, results in a special structure of the circuit with the possible attendant drawbacks.
An integrated circuit with an application circuit to be tested and a self-test circuit providing deterministic test samples is known from the publication “Using BIST control for pattern generation” by Gundolf Kiefer and Hans-Joachim Wunderlich (published in Proceedings International Test Conference 1997). This is achieved in that, in addition to a test sample generator, which is a feedback shift register and supplies pseudo-random samples, a logic element is provided which changes the output signal of this test sample generator in such a way that given deterministic test samples are produced. It can thereby be achieved that the circuit can be tested with predeterminable test samples and not only with samples that are quasi accidentally predetermined by the test sample generator.
SUMMARY OF THE INVENTION
It is an object of the invention to improve the integrated circuit described in the opening paragraph in such a way that a test of the application circuit with deterministic test samples is possible and that X signals simultaneously occurring within the circuit do not disturb the test results during testing, while no additional components need to be incorporated in the application circuit.
According to the invention, this object is solved in that the self-test circuit comprises a masking logic element which, during testing, blocks those bits of the output signals of the application circuit which, based on the circuit structure of the application circuit, have undefined states and applies only the other bits to the signature register.
The test samples generated by the self-test circuit are deterministic, i.e. they are predetermined test samples. These test samples are applied to the application circuit which changes the test samples in dependence upon the structure of the application circuit. The output signals of the application circuit thereby produced during testing are coupled to the signature register. The signature register combines these output signals, which originate from a plurality of test cycles, to one final result which represents a kind of signature and indicates whether the circuit operates without disturbances.
In this method, however, problems occur when components which are almost always present in the application circuit and have an analog or a memory behavior influence the output signals of the application circuit during testing. Then, so-called X signals are produced which supply a “don't care result”. In other words, such X-marked signals cannot be evaluated. Similarly, values which cannot be evaluated are produced for such signals in the signature register. This should be avoided.
According to the invention, this is achieved in that a masking logic element is provided. During testing of the circuit, the masking logic element blocks all those bits in the output signals of the application circuit which potentially comprise such X signals, i.e. all those bits which are influenced by a memorizing or analog behavior of components within the application circuit. The masking logic element only passes the other bits which are not influenced by such components to the signature register.
It is thereby ensured that those bits reaching the signature register during testing can be evaluated throughout. This in turn means that the signature result obtained in the signature register after passing through a plurality of test cycles can be completely evaluated and yields a reliable test result.
An essential advantage of the integrated circuit with a self-test circuit according to the invention is that the application circuit does not need to be modified for the test processes, i.e. it may be built up in such a way that it is optimal for use of the application circuit. The self-test circuit does not influence the normal operation of the application circuit in any way.
Furthermore, the self-test circuit according to the invention allows testing of the application circuit on the chip so that relatively slow bond pad connections do not disturb the test and the application circuit can be operated at maximum clock rates.
In accordance with an embodiment of the invention as defined in claim
2
, the test sample counter may be advantageously used for supplying a signal to the masking logic element informing this logic element which test sample within a plurality of test cycles is in the process of passing through the application circuit so that the masking logic element can accordingly block the bits in the output signal of the application circuit that are influenced during this passage by storing or analog components.
A shift cycle counter provided in accordance with a further embodiment of the invention as defined in claim
3
signalizes the state of shift registers in the application circuit to the masking logic element. It is thereby known which bits of the shift register should be blocked by the masking logic element and which should not be blocked.
These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.
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patent: 0780767 (1997-06-01), None
patent: 000800332 (1997-11-01), None
Chung Phung M.
Koninklijke Philips Electronics , N.V.
Ure Michael J.
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