Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2003-02-20
2004-09-28
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189011, C365S201000
Reexamination Certificate
active
06798701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device referred to as a system LSI a memory and a logic integrated on a common semiconductor substrate (chip). More specifically, the present invention relates to a configuration for externally testing an embedded memory allowing the number of input/output data bits to be varied with metal slicing.
2. Description of the Background Art
A DRAM-embedded system LSI having a DRAM (dynamic random access memory) and a logic device or a microprocessor integrated on a common semiconductor substrate (chip) has widely been used in recent years. Compared to a conventional system having a discrete DRAM and a logic device or a microprocessor mounted on a printed board with soldering or the like, such DRAM-embedded system LSI has following advantages.
(1) There is no restriction by a pin terminal. Therefore, width of a data bus between the DRAM and the logic device can be large, which will improve a data transfer rate, and accordingly, improve system performance.
(2) The data bus formed between the DRAM and the logic device is formed of on-chip interconnection lines, and the data bus has a capacitance smaller than the wires on the printed board. Therefore, an operation current in data transfer can be smaller, and high-speed data transfer can be achieved.
(3) A system is constituted by a single package. Accordingly, a data bus interconnection and a control signal interconnection are not needed externally, and an area occupied on the printed board can be smaller. Thus, the size of the system can be reduced.
FIG. 17
schematically shows an example of a configuration of a conventional DRAM-embedded system LSI. In
FIG. 17
, a DRAM-embedded system LSI
500
includes a logic
502
performing a prescribed processing, a DRAM macro
504
for storing at least data required by logic
502
, and a logic external bus
508
connecting logic
502
to an external device via a pad group
518
.
Logic
502
may be a dedicated logic device performing a prescribed processing, or may be a microprocessor, as far as it performs a process using the data stored in DRAM macro
504
.
DRAM macro
504
includes a DRAM core
510
storing data, a test interface circuit (TIC)
512
for performing a test through external, direct access to DRAM core
510
, and a selection circuit
517
for selecting either one of an internal logic bus
506
for logic
502
or an internal test bus
516
from test interface circuit
512
, and connecting the selected one to an internal memory bus
515
, which in turn is connected to DRAM core
510
. Test interface circuit
512
is coupled to pad group
518
via an external test bus
514
.
Buses
506
,
508
,
514
,
515
and
516
each include signal lines transmitting a control signal, an address signal and data. Since there is no restrictive condition by the pin terminal, internal logic bus
506
, internal memory bus
515
and internal test bus
516
can have a sufficient bus width.
Read data from DRAM core
510
is directly transferred to test interface circuit
512
and logic
502
without passing through select circuit
517
. In
FIG. 17
, however, the transfer path of the internal read data is not shown for the sake of simplicity.
In
FIG. 17
, logic external bus
508
and external test bus
514
are shown both being coupled to pad group
518
. External test bus
514
and logic external bus
508
, however, may be configured so as to be selectively connected to common pads in accordance with a test mode instruction signal (not shown).
FIG. 18
shows, in a list, signals for DRAM core
510
. In
FIG. 18
, DRAM core
510
receives, as operation control signals: a clock signal CLK; a clock enable signal CKE setting validity/invalidity of an internal clock signal in DRAM core
510
; a row activating signal /ACT activating an internal row selecting operation; a row inactivating signal /PRE for driving a selected row to a non-select state; an auto-refresh instruction signal /REFA instructing refresh of memory cell data in DRAM core
510
; a read operation instruction signal /RE instructing data read; and a write operation instructing signal /WR instructing a write data operation.
In addition, for addressing a memory cell, following signals are supplied to DRAM core
510
: a row address signal RA<
12
:
0
> of 13 bits; a column address signal CA<
3
:
0
> of 4 bits; an address signal for spare row space addressing RAsp for designating a spare memory cell row; and an address signal for spare column space addressing CAsp for designating a spare column.
Address signal for spare row space addressing RAsp and address signal for spare column space addressing CAsp are used to access spare memory cells in DRAM core
510
to determine the spare memory cells to be defective
on-defective, in a test performed before fuse-programming of a defective address.
These address signals for spare space addressing RAsp and CAsp designate a spare memory cell space when they are at H level, and designate a normal memory cell space at L level.
Write data D<
127
:
0
> of 128 bits and spare data SD<
1
:
0
> of 2 bits are supplied to DRAM core
510
, and read data Q<
127
:
0
> of 128 bits and spare data SQ<
1
:
0
> of 2 bits are output from the same. When a spare space is addressed, a spare memory cell for redundancy replacement is designated. The spare memory cell can directly be tested.
As shown in
FIG. 18
, DRAM core
510
has a larger number of input/output signals than a general-purpose DRAM of a discrete device. In this test operation as well, test interface circuit
512
generates signal/data as shown in
FIG. 18
to DRAM core
510
in accordance with a signal supplied from an external tester.
If test interface circuit
512
transfers the signal/data shown in
FIG. 18
to and from the external tester via pad group
518
using external test bus
514
, the number of these signal/data lines will be larger than that of pins of the external tester, and a test could not performed. In addition, even if a test can be performed, the number of devices that can be measured simultaneously is reduced, and cost for the test increases, because one device to be tested requires a large number of signal lines/data lines.
Test interface circuit
512
is provided in order to reduce the number of pins required in the test, and to implement an external, direct access to DRAM core
510
to readily test the same.
FIG. 19
shows, in a list, external signals for test interface circuit
512
. The signals shown in
FIG. 19
are transferred between an external test apparatus and test interface circuit
512
via external test bus
514
shown in FIG.
17
.
In
FIG. 19
, test clock signal TCLK and test clock enable signal TCKE are supplied to test interface circuit
512
. Test clock signal TCLK and test clock enable signal TCKE are used in a test operation mode, instead of clock signal CLK and clock enable signal CKE supplied to DRAM core
510
in a normal operation mode.
Further, a chip select signal ICS, a row address strobe signal /RAS, a column address strobe signal /CAS, and a write operation instruction signal /WE are supplied to test interface circuit
512
. A combination of logic levels, for example, at a rising edge of the test clock signal of these control signals including /CS, /RAs, /CAS and /WE, designates an operation mode of the DRAM core.
Test interface circuit
512
decodes these external control signals, and in accordance with the decoding result, selectively activates row activating signal /ACT, row inactivating signal /PRE, auto-refresh instruction signal /REFA, read operation instruction signal /RE, and write operation instruction signal /WE as shown in FIG.
18
.
As an address signal, an address signal AD<
12
:
0
> of 13 bits and an address signal for spare space addressing ADsp are supplied to test interface circuit
512
. A row address and a column address are applied via the same pads (terminals) in a t
Auduong Gene N.
Renesas Technology Corp.
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