Method of body contact for SOI mosfet

Details Method of body contact for SOI mosfet Method of body contact for SOI mosfet

2001-01-08

2004-09-07

Lee, Hsien Ming (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C438S586000, C438S622000, C438S672000

Reexamination Certificate

active

06787422

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of eliminating floating body effects in the fabrication of a silicon-on-insulator (SOI) MOSFET in the fabrication of integrated circuits.
2. Description of the Prior Art
An isolation technology that depends on completely surrounding devices by an insulator is referred to as silicon-on-insulator (SOI) technology. In general, the advantages of SOI technology include simple fabrication sequence, reduced capacitive coupling between circuit elements, and increased packing density. The SOI technology is discussed in
Silicon Processing for the VLSI Era
, Vol. 2, by S. Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, pp. 66-67. A disadvantage of SOI technology is inherent floating body effects due to the limitation in incorporating effective contact to the body. In bulk silicon MOSFETs, the bottom of the bulk silicon can be connected to a fixed potential. However, in an SOI MOSFET, the body is electrically isolated from the bottom of the substrate. The floating body effects result in drain current “kink” effect, abnormal threshold slope, low drain breakdown voltage, drain current transients, and noise overshoot. The “kink” effect originates from impact ionization. When an SOI MOSFET is operated at a large drain-to-source voltage, channel electrons cause impact ionization near the drain end of the channel. Holes build up in the body of the device, raising body potential and thereby raising threshold voltage. This increases the MOSFET current causing a “kink” in the current vs. voltage (I-V) curves. It is desired to eliminate floating body effects.
A number of patents present a variety of isolation methods for silicon-on-insulator and other types of MOSFETs. U.S. Pat. No. 5,504,033 to Bajor et al shows a process for forming both deep and shallow trenches in a SOI device; however, there is no requirement for the trenches to contact the substrate. U.S. Pat. Nos. 6,063,652 to Kim and 5,591,650 to Hsu et al show an SOI device having a shallow trench isolation (STI) formed entirely through the silicon to the oxide layer. U.S. Pat. No. 5,874,328 to Liu et al discloses trench isolation through a source/drain region. U.S. Pat. No. 5,674,760 to Hong discloses an isolation structure, but not in SOI technology. U.S. Pat. No. 5,930,605 to Mistry et al discloses a Schottky diode connection between the body and one of the source/drain regions.
SUMMARY OF THE INVENTION
Accordingly, a primary object of the invention is to provide a process for forming a silicon-on-insulator MOSFET in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming a silicon-on-insulator MOSFET while eliminating floating body effects.
Another object of the invention is to provide a process for forming a silicon-on-insulator MOSFET while eliminating floating body effects by providing contact to the body of the transistor.
In accordance with the objects of the invention, a method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is achieved. A silicon-on-insulator substrate is provided comprising a semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched into the silicon layer wherein the first trench extends partially through the silicon layer and does not extend to the underlying oxide layer. Second trenches are etched into the silicon layer wherein the second trenches extend fully through the silicon layer to the underlying oxide layer and wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer between the second trenches. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. In the same step, a second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.
Also in accordance with the objects of the invention, a silicon-on-insulator device in an integrated circuit is achieved. The device comprises a silicon layer overlying an oxide layer on a silicon semiconductor substrate. Shallow trench isolation regions extend fully through the silicon layer to the underlying oxide layer wherein the shallow trench isolation regions separate active areas of the semiconductor substrate. A second isolation trench lies within each of the active areas and extends partially through the silicon layer wherein the second isolation trench does not extend to the underlying oxide layer. Gate electrodes and associated source and drain regions lie in and on the silicon layer between the shallow trench isolation regions and covered with an interlevel dielectric layer. First conducting lines extend through the interlevel dielectric layer to the underlying source and drain regions. A second conducting line within each of the active areas extends through the interlevel dielectric layer wherein the second conducting line contacts both the second trench and one of the shallow trench isolation regions.


REFERENCES:
patent: 5504033 (1996-04-01), Bajor et al.
patent: 5591650 (1997-01-01), Hsu et al.
patent: 5638932 (1997-06-01), Mizukami
patent: 5674760 (1997-10-01), Hong
patent: 5874328 (1999-02-01), Liu et al.
patent: 5930605 (1999-07-01), Mistry et al.
patent: 6063652 (2000-05-01), Kim
patent: 6341087 (2002-01-01), Kunikiyo
patent: 6345399 (2002-02-01), Jamison et al.
patent: 6368941 (2002-04-01), Chen et al.
patent: 6406948 (2002-06-01), Jun et al.
patent: 2001/0050397 (2001-12-01), Matsumoto et al.
patent: 2002/0047155 (2002-04-01), Babcock et al.
patent: 2001111056 (2001-04-01), None
US 6,384,465, 5/2002, Iwamatsu et al. (withdrawn)*
Wolf S. “Silicon Processing for the VLSI-ERA: vol. 2-Process Integration”, 1990, Lattice Pr., vol. 2 pp. 176, 189-195.*
S. Wolf, “Silicon Processing for the VLSI Era”, vol. 2, Lattice Press, Sunset Beach, CA, c. 1990, pp. 66-67.

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