Surface alteration of metal interconnect in integrated...

Details Surface alteration of metal interconnect in integrated... Surface alteration of metal interconnect in integrated...

2003-03-25

2004-09-21

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S761000, C257S767000

Reexamination Certificate

active

06794755

ABSTRACT:

FIELD
An embodiment of the invention relates generally to the field of semiconductor technology and, more specifically, to the formation of interconnects in an integrated circuit.
BACKGROUND
In the formation of electronic circuitry, electromigration of metal interconnects must be considered.
FIG. 1
illustrates a metal interconnect formed according to a conventional technique. Referring to
FIG. 1
, an interlayer dielectric (ILD)
102
is deposited on an etch-stop layer
104
, typically silicon nitride. A via
106
and trench
107
are patterned into the ILD
102
according to well-known dual damascene techniques. A barrier layer
108
may be formed on the bottom and sidewalls of the via
106
and the trench
107
. The via
106
and trench
107
are then filled with an electrically conductive material, such as copper and planarized to the top of the ILD
102
, thus forming a copper interconnect
110
. An etch-stop layer
112
, is deposited over the planarized ILD
102
, the planarized barrier layer
108
, and the planarized interconnect
110
. Consequently, a second ILD
114
, second barrier layer
118
, and second interconnect
116
may be formed, the second barrier layer
118
and second interconnect
116
connecting to the first interconnect
110
to provide electrical connection between interconnects
110
and
116
. The process may repeat itself for additional ILD/ interconnect layers.
The typical copper interconnect shown in
FIG. 1
suffers from problems. As current flows through the copper interconnect
110
, the force of the flowing electrons in the current dislodges copper ions within the interconnect
110
, a phenomena generally known as “electromigration”. The dislodged copper ions tend to migrate in a direction that has the least resistance to their movement. The interface
120
between the top of the copper interconnect
110
with the bottom of the etch-stop layer
112
is commonly the area of least resistance. In other words, the etch-stop layer
112
does not significantly prevent electromigration at the top of the interconnect
110
.
As integrated circuits become smaller in size, interconnects must also become smaller. Consequently, modern interconnects must have higher current densities to maintain proper electrical performance. Unfortunately, the higher that an interconnect's current density increases, so does the tendency to cause electromigration at the top of the interconnect
110
. In other words, because of the increased density of modern interconnects, dislodged ions will be even more inclined to seek paths of least resistance than in the past, thus increasing the tendency for electromigration to occur at the top of interconnect
110
. Because the top of the interconnect is especially vulnerable to the electromigration effect, modern interconnects are suffering electromigration at the top more severely than in the past.
Some attempts have been made to address this problem, such as doping, cleaning, or roughening the top of the copper interconnect. However these approaches result in limited gains for electromigration performance and low adhesion strengths or tend to contaminate the entire interconnect with a dopant species resulting in a high electrical resistivity.


REFERENCES:
patent: 6147000 (2000-11-01), You et al.
patent: 6268291 (2001-07-01), Andricacos et al.
patent: 6342444 (2002-01-01), Higashi et al.
patent: 6426289 (2002-07-01), Farrar
patent: 6521523 (2003-02-01), Lee et al.

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