Semiconductor memory device capable of preventing coupling...

Details Semiconductor memory device capable of preventing coupling... Semiconductor memory device capable of preventing coupling...

2002-11-19

2004-05-11

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Read/write circuit

Noise suppression

C365S230040, C365S230060

Reexamination Certificate

active

06735136

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2001-71800, filed on Nov. 19, 2001.
BACKGROUND
1. Technical Field
The present invention relates to semiconductor memory devices and, in particular, to a semiconductor memory device comprising a shared sense amplifier structure, which prevents coupling noise between adjacent bit lines in different columns.
2. Description of Related Art
FIG. 1
is a block diagram of a semiconductor memory device. A semiconductor memory device
10
comprises a memory block
12
having a plurality of columns. Each column comprises a pair of bit lines and a plurality of memory cells such as DRAM, SRAM, or EEPROM cells.
For example, first through fourth columns each comprise a pair of bit lines DB
0
and DBb
0
, UB
0
and UBb
0
, DB
1
and DBb
1
, and UB
1
and UBb
1
, respectively. Odd-numbered and even-numbered columns are alternatively arranged in the memory block
12
. Eight pairs of bit lines are shown in
FIG. 1
for purposes of illustration, and it is to be understood that the memory can comprise additional pairs of bit lines arranged therein.
Each of the bit line pairs DB
0
/DBb
0
, DB
1
/DBb
1
, DB
2
/DBb
2
, and DB
3
/DBb
3
, of the odd-numbered columns (first, third, fifth and seventh columns) is connected to a corresponding bit line precharging and equalizing circuit
14
, bit line isolating circuit
16
, and sense amplifier
18
.
For example, the bit line precharging and equalizing circuit
14
for bit line pair DB
0
/DBb
1
comprises three NMOS transistors M
1
, M
2
, and M
3
. The bit line precharging and equalizing circuit
14
precharges and equalizes the bit lines to a predetermined voltage (e.g., ½ VCC voltage) in response to a control signal PEQi. Each bit line isolating circuit
16
is connected to a corresponding bit line pair to selectively connect the bit lines to a corresponding sense amplifier
18
. Each bit line isolating circuit
16
comprises NMOS transistors M
4
and M
5
that are simultaneously activated/deactivated in response to a control signal PISOi.
Each sense amplifier
18
comprises a latch-type sense amplifier and is connected to a corresponding bit line pair and to voltage lines LA and LAb. The voltage line LAb is connected to ground voltage through an NMOS transistor M
10
, which is activated in response to a control signal LANG output from a control block
20
. The voltage line LA is connected to power supply voltage for array Varray through a PMOS transistor M
11
, which is activated in response to a control signal LAPG output from the control block
20
. The control block
20
generates the control signals LANG and LAPG in response to a complementary sense enable signal {overscore (BLSA_en)}.
Further, each bit line pair UB
0
/UBb
0
, UB
1
/UBb
1
, UB
2
/UBb
2
, and UB
3
/UBb
3
(which correspond to even-numbered columns) are connected to a corresponding bit line precharging and equalizing circuit
22
, a bit line isolating circuit
24
, and a sense amplifier
26
. The circuits
22
,
24
and
26
have the same configurations as circuits
14
,
16
and
18
.
FIG. 2
is a circuit diagram of the control block
20
of FIG.
1
.
FIG. 3
depicts exemplary waveforms of the control signals of FIG.
2
. The control block
20
comprises an inverter INV
1
, a delay element
21
, and a NAND gate G
1
, and generates control signals LANG and LAPG in response to the sense enable signal {overscore (BLSA_en)}. When the sense enable signal {overscore (BLSA_en)} transitions from a high level to a low level, the control signal LANG is activated at a high level as illustrated in FIG.
3
. In response to the activation of the control signal LANG, the NMOS transistor M
10
(
FIG. 1
) is activated, thereby supplying ground voltage to the voltage line LAb. The control signal LANG is delayed by delay element
21
. The delayed control signal and the control signal LANG are NAND gated by gate G
1
to generate the control signal LAPG. When the control signal LAPG transitions from a high level to a low level, the PMOS transistor M
11
(shown in
FIG. 1
) is activated, thereby supplying power supply voltage for array Varray to the voltage line LA.
In the semiconductor memory device
10
, coupling noise is generated between adjacent bit lines in adjacent columns, as indicated by the dotted circles that connect adjacent bit lines in FIG.
1
. The bit line pair of each column, which comprises a true bit line and a complement bit line, receives data from a memory cell in response to the activation of a row or a word line connected to the memory cell.
FIG. 4A
is an exemplary diagram illustrating coupling noise that is generated in the semiconductor memory device
10
. For example, when the memory cell storing data ‘1’ is sensed, a precharge voltage of the true bit line UB
0
of the second column connected to the memory cell is increased by the voltage corresponding to the data ‘1’. The complement bit line UBb
0
of the true bit line UBO maintains the precharged voltage. When the control signal LANG is activated, a voltage of a bit line having a relatively lower voltage, that is, the voltage of the complement bit line UBb
0
, is lowered to ground voltage. When the control signal LAPG is activated, a voltage of a bit line having a relatively higher voltage, that is, the voltage of the true bit line UB
0
is increased to the power supply voltage for array Varray.
When a memory cell connected to a true bit line (e.g., the true bit line DB
1
of the third column) of an adjacent column to the second column stores data ‘1’, the precharged voltage of the true bit line DB
1
is increased by the voltage corresponding to the data ‘1’. The corresponding complement bit line DBb
1
maintains the precharged voltage. When the control signal LANG is activated, a voltage of a bit line having a relatively lower voltage, that is, the voltage of the complement bit line DBb
1
, is lowered to the ground voltage. When the control signal LAPG is activated, a voltage of a bit line having a relatively higher voltage, that is, the voltage of the true bit line DB
1
is increased to the power supply voltage for array Varray.
A coupling capacitor is formed between the adjacent bit lines UBb
0
and DB
1
of the adjacent pairs of bit lines UB
0
and UBb
0
, and DB
1
and DBb
1
of the second and third columns. When the voltage of the complement bit line UBb
0
of the second column is lowered to the ground voltage in response to the activation of the control signal LANG, the voltage of the true bit line DB
1
of the third column is instantly lowered by the coupling capacitor, as illustrated in FIG.
4
A. This phenomenon is called “coupling noise”, which generates erroneous data.
The coupling noise also occurs when a memory cell storing data ‘0’ is sensed. Referring to
FIG. 4B
, when the memory cell storing data ‘0’ is sensed, the true bit line UB
3
of the eighth column connected to the memory cell stores the data ‘0’. The precharged voltage of the true bit line UB
3
is lowered by the voltage corresponding to the data ‘0’, while the corresponding complement bit line UBb
3
maintains the precharged voltage. In response to the activation of the control signal LANG, a voltage of a bit line having a relatively lower voltage, that is, the voltage of the true bit line UB
3
, is lowered to the ground voltage. In response to the activation of the control signal LAPG, a voltage of a bit line having a relatively higher voltage, that is, the voltage of the complement bit line UBb
3
, is increased to the power supply voltage for array Varray.
When the memory cell connected to a column (e.g., the seventh column) that is adjacent to the eighth column stores data ‘0’, the precharged voltage of the true bit line DB
3
of the seventh column is lowered by the voltage corresponding to the data ‘0’. The corresponding complement bit line DBb
3
maintains the precharged voltage. In response to the activation of the control signal LANG, a voltage of a bit line having a relatively lower voltage, that is, the voltage of the true bit l

Affiliated with

Also associated with

Rating

Semiconductor memory device capable of preventing coupling... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device capable of preventing coupling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device capable of preventing coupling... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3220596