Method of manufacturing semiconductor memory device...

Details Method of manufacturing semiconductor memory device... Method of manufacturing semiconductor memory device...

2000-10-16

2004-09-14

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C138S097000, C138S097000, C138S097000, C138S097000

Reexamination Certificate

active

06790718

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a semiconductor memory device such as a flash EEPROM (Electrical erasable programable read only memory) capable of electrically writing and erasing data, and such a semiconductor memory device.
2. Description of the Related Art
Flash EEPROMs, or nonvolatile semiconductor memory devices capable of electrically writing and erasing data, have a plurality of cell transistors disposed in a memory cell assembly for storing data and having floating gate electrodes and control gate electrodes, and a plurality of select transistors disposed in the memory cell assembly for selecting the cell transistors. In more practical flash EEPROMs, the transistors of a peripheral circuit such as a logic operation circuit are disposed on the same substrate as the cell and select transistors.
One known flash EEPROM comprises parallel arrays of cell transistors connected to respective data lines for writing and reading data, and a plurality of select transistors connected in series with the respective arrays of cell transistors, as shown in
FIG. 1
of the accompanying drawings. The flash EEPROM shown in
FIG. 1
has a small device area and can be manufactured in a relatively small number of fabrication steps though the speed at which memory cells are accessed is not significantly high. Therefore, the flash EEPROM shown in
FIG. 1
is used as memories for IC cards, for example, which need to be highly integrated and low in cost.
The flash EEPROM shown in
FIG. 1
as an example of a conventional semiconductor memory device and a method of manufacturing same will be described below.
The flash EEPROM shown in
FIG. 1
has a memory cell assembly comprising a plurality of cell transistors M
101
-M
164
, M
201
-M
264
, M
301
-M
364
, M
401
-M
464
arranged in a grid pattern. The memory cell assembly is divided into a plurality of blocks each comprising a predetermined number of (
64
in
FIG. 1
) cell transistors, parallel to data lines D
1
-D
4
. In each of the blocks, the cell transistors have respective sources connected in common and respective drains connected in common. The cell transistors are also arranged in transverse arrays across the data lines, and the cell transistors in those transverse arrays have respective control gate electrodes connected in common to word lines W
1
-W
64
for selecting positions to storing data.
Each of the blocks has two select transistors for selecting a predetermined number of parallel-connected cell transistors. First select transistors Q
11
, Q
21
, Q
31
, Q
41
shown in
FIG. 1
are inserted between the drains of the cell transistors and respective contacts J
1
-J
4
on the data lines, and second select transistors Q
12
, Q
22
, Q
32
, Q
42
shown in
FIG. 1
are inserted between the sources of the cell transistors and common source CS kept at ground potential. The first select transistors in the respective blocks have gate electrodes connected in common to first selection gate line SG
1
, and the second select transistors in the respective blocks have gate electrodes connected in common to second selection gate line SG
2
.
As shown in
FIG. 2
of the accompanying drawings, the blocks of the memory cell assembly are separated by a field oxide film. The cell transistors, represented by M
101
-M
164
, M
201
-M
264
in
FIG. 2
, have source regions S and drain regions D formed in common in the respective blocks. Those common source regions S and drain regions D are also used as interconnections connecting the cell transistors parallel to each other in each of the blocks.
Floating gate electrodes (not shown) and control gate electrodes are disposed at spaced intervals on and across source regions S and drain regions D. The control gate electrodes are connected in common in respective transverse arrays in
FIG. 2
, and also used as the word lines. Regions directly below the control gate electrodes sandwiched between the source regions and the drain regions serve as channel regions where currents flow.
The drain regions of the cell transistors have ends connected to source regions S of the first select transistors, which are represented by Q
11
, Q
21
in FIG.
2
. The first select transistors have respective drain regions D that are positioned across first selection gate line SG
1
from source regions S of the first select transistors. The contacts, which are represented by J
1
, J
2
in
FIG. 2
, for connection to the data lines are disposed on drain regions D of the first select transistors. Though the second select transistors are omitted from the illustration in
FIG. 2
, the second select transistors are arranged in the same manner as the first select transistors and connected to ends of the source regions of the cell transistors.
For writing or erasing data, a cell transistor is selected at the point of intersection of a data line and a word line to which certain voltages are applied. The data is stored in or erased from the selected cell transistor by a charge introduced into or removed from the floating gate electrode of the selected cell transistor. The data stored in the cell transistor is read by detecting a change in a threshold voltage that is caused by introducing a charge into the floating gate electrode of the selected cell transistor.
A conventional method of manufacturing the flash EEPROM shown in
FIGS. 1 and 2
will be described below with reference to
FIGS. 3 through 10
of the accompanying drawings. The structure of a select transistor shown in
FIGS. 3 through 10
is taken along line A-A′ of
FIG. 2
, and the structure of a cell transistor shown in
FIGS. 3 through 10
is taken along line B-B′ of FIG.
2
.
First, a thin SiO
2
film and a silicon nitride (Si
3
N
4
) film is formed on substrate
101
of p-type semiconductor and patterned to a predetermined shape, and its openings are selectively oxidized to form field oxide film
106
as an inactive region for separating components. Then, gate insulating film
102
a
of the select transistor and tunneling oxide film
102
b
of the cell transistor are grown on the surface of substrate
101
by thermal oxidization. At this time, since the select transistor requires a high withstand voltage, the following multi-oxidizing process is performed: First, the surface of substrate
101
is thermally oxidized in order to form an oxide film thinner than a desired film thickness. The thickness of the oxide film is smaller than the desired film thickness by a thickness which will be added when tunneling oxide film
102
b
is subsequently to be formed.
Then, a photoresist is formed in the select transistor area, and the oxide film in the cell transistor area is etched away. Thereafter, the photoresist is removed, and the assembly is thermally oxidized until the oxide film in the cell transistor area gains a desired film thickness, growing the gate insulating film
102
a
of the select transistor and tunneling oxide film
102
b
of the cell transistor to respective desired film thicknesses (see FIG.
3
).
Then, first N-type polysilicon film
103
, which serves as the floating gate electrode of the cell transistor, is grown on the surface formed so far. Pad oxide film
104
is grown on first N-type polysilicon film
103
by CVD (Chemical Vapor Deposition), and second N-type polysilicon film
105
is grown on pad oxide film
104
. Second N-type polysilicon film
105
will be used only as a mask in a subsequent ion implantation step. Therefore, second N-type polysilicon film
105
may be replaced with an amorphous silicon film or a silicon nitride film.
Then, first N-type polysilicon film
103
, pad oxide film
104
, and second N-type polysilicon film
105
are patterned to respective shapes. The width of first N-type polysilicon film
103
which is formed at this time determines the channel widths of the cell transistor and the select transistor (see FIG.
4
).
Using second N-type polysilicon film
105
as a mas

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