Synchronous memory device having a plurality of clock input buff

Details Synchronous memory device having a plurality of clock input buff Synchronous memory device having a plurality of clock input buff

1998-05-18

1999-08-17

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365194, 365233, G11C 700

Patent

active

059403306

ABSTRACT:
A synchronous memory device having a plurality of clock input buffers includes a first clock input buffer for generating an enable signal of a data output buffer, and a second clock input buffer for generating a signal to latch external input signals (i.e., an address signal, a row address strobe (RAS) signal, a column address strobe (CAS) signal and so on). As a result, the synchronous memory device achieves a clock access time of a high speed, and reduces a current consumption in a standby mode.

REFERENCES:
patent: 5659507 (1997-08-01), Yabe et al.
patent: 5687134 (1997-11-01), Sugawara et al.
patent: 5801554 (1998-09-01), Momma et al.
patent: 5815462 (1998-09-01), Konishi et al.

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