Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
2002-09-12
2004-09-14
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S790000
Reexamination Certificate
active
06790749
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a thin film transistor (TFT) and to a process for fabricating the same. The present invention also relates to a process for fabricating an insulated gate semiconductor device on an insulator substrate and to a process for fabricating an integrated circuit (IC) obtained by assembling a plurality of said insulated gate semiconductor devices on an insulator substrate. The term “insulator substrate” as referred herein means any article having an insulating surface, and, if not particularly stated, it encompasses not only those made of insulating materials such as glass, but also articles having thereon an insulator layer and made of a material such as a semiconductor and a metal. The semiconductor device according to the present invention is useful as TFTs of active matrices of liquid crystal displays, driver circuits of image sensors, or SOI (silicon on insulator) integrated circuits and conventional semiconductor integrated circuits (e.g., microprocessors and micro controllers, micro computers, and semiconductor memories).
2. Prior Art
Recently, intensive study is performed on the process for fabricating an insulated gate semiconductor device (MOSFET) on an insulator substrate. The integrated circuits (ICs) of this type being established on an insulator substrate are advantageous considering their suitability to high speed drive, because such ICs on an insulator need not suffer stray capacitance. In contrast to these ICs, the operation speed of a conventional IC is limited by a stray capacitance, i.e., a capacitance between the connection and the substrate. The MOSFETs having formed on an insulator substrate and comprising a thin film active layer is called a thin film transistor (TFT). Those TFTs are indispensable in forming multilayered integrated circuits. At present, a TFT can be found in a conventional semiconductor IC, for example, as a load transistor of an SRAM.
Some of the recent products, for example, driver circuits for optical devices such as liquid crystal displays and image sensors, require a semiconductor IC to be formed on a transparent substrate. TFTs can be found assembled therein, however, the ICs must be formed over a wide area, and a low temperature process for fabricating TFTs is thereby required. Furthermore, in devices having a plurality of terminals each connected with semiconductor ICs on an insulator substrate, for instance, it is proposed to reduce the mounting density by forming the lower layers of the semiconductor IC or the entire semiconductor IC itself monolithically on the same insulator substrate.
Conventionally, TFTs of high quality have been obtained by thermally annealing an amorphous or semi-amorphous film, or a microcrystalline film at a temperature in the range of from 450 to 1,200° C. to produce a high performance semiconductor film (i.e., a semiconductor film having sufficiently high mobility). An amorphous TFT using an amorphous material for the semiconductor film can also be fabricated; however, its application field is greatly limited because of its inferior operation speed ascribed to an extremely low mobility of 5 cm
2
/Vs or even lower, about 1 cm
2
/Vs in general, or because of its inability of providing a P-channel TFT (PTFT). A TFT having a mobility of 5 cm
2
/Vs or higher is available only after annealing the semiconductor film at a temperature in the range of from 450 to 1,200° C. A PTFT can be fabricated only after subjecting the film to such annealing treatments.
However, in a thermal process involving heating at a high temperature, in particular, only strictly selected substrate material can be used. More specifically, a so-called high temperature process which involves high temperature heating in the range of from 900 to 1,200° C. is advantageous, because it allows the use of a high quality film obtainable by thermal oxidation as a gate dielectric, but substrates applicable to the high temperature process are confined to those made from expensive materials such as quartz, sapphire, and spinel, which are not suited for substrates to use in large area applications.
In contrast to the high temperature process above, a low temperature process, in which maximum temperature is in the range of from 450 to 750° C., allows the use of substrate materials selected from a wider variety. However, such a process requires long annealing, and moreover, the sheet resistance of the source/drain remains high due to insufficient activation of the impurities. There is also an attempt of crystallizing the active layer and of activating source/drain by irradiating a laser beam and the like (this process is denoted as “laser process”, hereinafter), however, it has been found also difficult to lower the sheet resistance. In fabricating a TFT having a field mobility higher than 150 cm
2
/Vs, in particular, it is essential to achieve a sheet resistance of not higher than 200 &OHgr;/cm
2
.
It is also well known to use TFTs in devices such as active matrix-driven liquid crystal display devices and image sensors comprising glass substrates having integrated elements thereon.
FIG. 9
schematically shows a cross sectional view of a conventional TFT.
FIG. 12
shows schematically a cross sectional view of another conventional TFT and an example of the step sequential process for fabricating the same. FIG.
9
(A) shows an insulated gate field effect transistor (referred to simply hereinafter as a “TFT”) using a thin film silicon semiconductor provided on a glass substrate. Referring to FIG.
9
(A), a silicon oxide film
62
about 2,000 Å in thickness as a base is formed on a glass substrate
61
, and an active layer comprising a silicon semiconductor film having source/drain regions
63
and
65
together with a channel forming region
64
is formed on the silicon oxide film
62
. An amorphous or crystalline (polycrystalline or microcrystalline) silicon semiconductor layer is provided at a thickness of about 1,000 Å.
A silicon oxide film
66
about 1,000 Å in thickness as a gate insulator film is formed on the active layer. An aluminum gate contact
67
is established thereon, and it is surrounded by an oxide layer
68
about 2,000 Å in thickness formed by anodic oxidation. An interlayer insulator
69
is formed using silicon oxide, etc., and source/drain contacts
70
and
71
, as well as a contact hole
72
to the gate contact
67
are established therein. In FIG.
9
(A), the contact hole
72
connected to the gate contact
67
is not in the same plane as that on which the source/drain contacts
70
and
71
are located, but is provided either beyond or at the front of the plane.
The structure shown in FIG.
9
(A) is characterized in that an offset gate region can be formed in a self aligned manner by controlling the anodic oxidation of the aluminum gate contact
67
. The thickness
73
of the oxide layer
68
around the gate contact
67
depends on this controlled thickness which results from anodic oxidation. More specifically, an offset region corresponding to the thickness of the oxide layer
68
can be established by implanting impurity ions for forming source/drain regions after forming the oxide layer
68
.
However, because of the diffusion of the impurities, the boundary between the channel forming region
64
and the source/drain regions
63
and
65
in practice is located at a portion nearer to the channel forming portion than the portion corresponding to the edge of the oxide layer
68
. Thus, the thickness of the oxide layer
68
must be determined taking the influence of diffusion into consideration. In general, the oxide layer
68
must be formed thicker than the length of the desired offset gate.
The contact holes connected to the source/drain regions
63
and
65
must be perforated with care not to be overetched. An excessive etching beyond the boundary between the silicon oxide film
66
and into the peripheral portion of the contact hole allows aluminum to diffuse into the etched peripheral portion upon form
Takemura Yasuhiko
Teramoto Satoshi
Zhang Hongyong
Coleman W. David
Costellia Jeffrey L.
Nixon & Peabody LLP
Semiconductor Energy Laboratory Co,. Ltd.
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