Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-06-13
2004-07-13
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S138000, C438S528000
Reexamination Certificate
active
06762097
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a power semiconductor device such as a diode, a MOSFET (field-effect insulated gate transistor) and an IGBT (a conductivity modulation-type transistor) for use in a power converter or the like and, more particularly, to a semiconductor device and a method for manufacturing the same that are suitable for the use of a FZ (floating zone) wafer.
2. Description of Related Art
An epitaxial diode in
FIG. 6
is manufactured by using an epitaxial wafer that is formed by growing a low-concentration n-type epitaxial layer, which functions as an n
−
drift layer
3
, on a high-concentration n-type silicon substrate forming an n
+
cathode layer
1
. The n
−
drift layer
3
carries drift current in an ON state. In a blocking mode (an OFF state), a depletion layer spreads into the n
+
cathode layer
1
from a pn junction between the n
−
drift layer
3
and a p
+
anode layer
4
to thereby assure a withstand voltage. The n
+
cathode layer
1
has a function of preventing the depletion layer from reaching a cathode electrode
9
in the blocking mode and achieving a favorable ohmic contact with the cathode electrode
9
. The epitaxial diode using the epitaxial wafer has the high-concentration n-type silicon substrate and the n
−
drift layer
3
, which is grown on the high-concentration n-type silicon substrate by an epitaxial method. Therefore, an impurity concentration inclines sharply in the n
+
cathode layer
1
and at the boundary between the n
+
cathode layer
1
and the n
−
drift layer
3
, as shown in the graph representing the longitudinal dependency of a doping concentration in FIG.
6
. Thus, there is a favorable tradeoff relationship between a forward voltage and the withstand voltage. The epitaxial wafer, however, is expensive and, therefore, it is costly to manufacture the epitaxial diode.
On the other hand, a DW diode in
FIG. 7
is manufactured from a DW wafer that is fabricated by diffusing a high-concentration phosphorus from the reverse side of a low-concentration n-type silicon substrate (FZ wafer), which functions as the n
−
drift layer
3
, to from an n
+
cathode layer
1
a
. The DW wafer is less expensive than the epitaxial wafer because the DW wafer does not require a growing step by an epitaxial method. Thus, the use of the DW wafer can reduce the cost of manufacturing the DW diode. As shown in the graph representing the longitudinal dependency of doping concentration in
FIG. 7
, however, the impurity concentration inclines gently in the n
+
cathode layer
1
a
and at the boundary between the n
+
cathode layer and the n
−
drift layer
3
. Therefore, there is an unfavorable tradeoff relationship between the forward voltage and the withstand voltage.
A non-punch through IGBT in
FIG. 8
is manufactured by using an inexpensive FZ wafer forming an n
−
drift layer
33
. An element active region (e.g., a p
+
base region
34
, an n
+
emitter region
35
, a gate oxide film
36
or a gate electrode
37
) and an emitter electrode
38
are formed at the right side of the FZ wafer. The reverse side of the wafer is treated to reduce it to a predetermined thickness and, then, the reverse side of the wafer is implanted with boron ions, a portion of the implanted ions being activated by annealing at a low temperature of not greater than 400° C. This forms a p
+
collector layer
31
. To acquire a sufficient withstand voltage in a forward blocking mode, the n
−
drift layer
33
must have enough thickness to prevent the depletion layer spreading from the pn junction between the p
+
base region
34
and the n
−
drift layer
33
from reaching the p
+
collector layer
31
. If the n
−
drift layer
33
is thick, however, the resistance is increased to significantly lower the voltage in the ON state of the IGBT. This makes it difficult to achieve a large volume of power and increases the number of carriers accumulated in the n
−
drift layer
33
. In addition, there is a great turnoff loss. Although the non-punch through IGBT can be manufactured at a low cost, it cannot achieve high performance.
On the other hand, a punch through IGBT in accordance with
FIG. 9
is manufactured by using an epitaxial wafer, which is fabricated by growing a high-concentration n-type epitaxial layer functioning as an n
+
buffer
32
on a high-concentration p type substrate forming a p
+
collector layer
31
a
, and growing a low-concentration n-type epitaxial layer functioning as an n
−
drift layer
33
a
on the high-concentration n-type epitaxial layer. In a forward blocking mode, a depletion layer spreads slowly in the high impurity concentration n
+
buffer layer
32
, and it is therefore possible to acquire a high withstand voltage even in the thin n
−
drift layer
33
a
. Therefore, the voltage of the punch through IGBT is lowered by a smaller degree in the ON state, as compared with the non-punch through IGBT with the same withstand voltage. In addition, the punch through IGBT increases the current capacity and reduces the turnoff loss. However, it costs more to manufacture the punch through IGBT, since there is the need to use an epitaxial wafer.
A power semiconductor device, such as a diode or a MOSFET, has recently achieved high characteristics, but it is still desired to further reduce costs. To reduce the costs, it is advantageous to adopt an inexpensive FZ wafer in a wafer process. In order to achieve high characteristics, the reverse side of the FZ wafer, which has a surface active region, such as the p
+
anode layer
4
and the anode electrode
8
thereof, is treated to reduce it to a predetermined thickness; phosphorus and arsenic ions are implanted from the reverse side; and an annealing process is performed to thereby activate the impurities and form an n
+
cathode layer. Since the maximum concentration point can be set at a deep portion by the ion implantation method, the impurity concentration inclines sharply in the n
+
cathode layer and at the boundary between the n
+
cathode layer and the n
−
drift layer. Therefore, the power semiconductor device can be expected to achieve high characteristics of the same level as achieved by an epitaxial diode.
The annealing temperature should be not less than about 1000° C. to activate the phosphorus or arsenic atoms sufficiently in the silicon wafer. Thus, the annealing must be completed before the aluminum anode electrode
8
, which has a low fusing point (about 700° C.), is adhered to the surface of the wafer. Even if the annealing is performed before the adhesion of the anode electrode
8
, the wafer bows greatly when the thin wafer (after it has been treated to reduce its thickness) is annealed at high temperatures of 1000° C. or more. It is therefore impossible to perform a photolithography process to form the anode electrode
8
at a subsequent stage. For this reason, the inexpensive FZ wafer cannot be used in the wafer process. This problem applies not only to the above-mentioned longitudinal diode cathode layer, but also to the formation of a general ohmic contact layer (high impurity concentration layer) at the outermost surface of the reverse side, such as a drain layer of a longitudinal MOSFET or a collector layer of an IGBT (conductivity modulation-type MOSFET) of a non-punch through IGBT.
Accordingly, it is an object of the present invention to provide a semiconductor device, which can be manufactured with less trouble by using the inexpensive FZ wafer in the wafer process and has a sharp impurity concentration in a high impurity concentration layer at the outermost portion of the reverse side and at the boundary between the high impurity concentration layer and a low impurity concentration drift layer, thereby achieving both low cost and high performance.
In recent years, power semiconductor devices such as IGBT devices ach
Fujihira Tatsuhiko
Takei Manabu
Fuji Electric & Co., Ltd.
Rossi & Associates
Trinh Michael
LandOfFree
Semiconductor device and method for manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3212549