Fully depleted SOI transistor with elevated source and drain

Details Fully depleted SOI transistor with elevated source and drain Fully depleted SOI transistor with elevated source and drain

2001-02-09

2004-09-07

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S486000, C257S021000, C257S431000

Reexamination Certificate

active

06787424

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This patent application is related to U.S. application Ser. No. 09/405,831, now issued U.S. Pat. No. 6,248,637, filed on Sep. 24, 1999, by Yu, entitled “A Process for Manufacturing MOS Transistors Having Elevated Source and Drain Regions,” U.S. application Ser. No. 09/397,217, filed on Sep. 16, 1999, by Yu et al., now issued U.S. Pat. No. 6,403,433, entitled “Source/Drain Doping Technique for Ultra-Thin-Body SOI MOS Transistors,” and U.S. application Ser. No. 09/384,121, filed on Aug. 27, 1999, by Yu, now issued U.S. Pat. No. 6,265,293, entitled “CMOS Transistors Fabricated in Optimized RTA Scheme.” This patent application is also related to U.S. application Ser. No. 09/609,613, filed on Jul. 5, 2000 herewith by Yu entitled, now issued U.S. Pat. No. 6,399,450, “A Process for Manufacturing MOS Transistors having Elevated Source and Drain Regions”. This patent application is also related to U.S. Pat. application Ser. No. 09/781,039, filed on an even date herewith by Yu, entitled “Low Temperature Process to Locally Form High-K Gate Dielectrics,” U.S. Pat. application Ser. No. 09/779,985, filed on an even date herewith by Yu, entitled “Replacement Gate Process for Transistor Having Elevated Source and Drain,” U.S. Pat. application Ser. No. 09/779,986, filed on an even date herewith by Yu, entitled “A Low Temperature Process For a Thin Film Transistor,” U.S. Pat. application Ser. No. 09/779,988, filed on an even date herewith by Yu, entitled “Low Temperature Process for Transistors with Elevated Source and Drain,” and U.S. Pat. application Ser. No. 09/779,987, now issued U.S. Pat. No. 6,403,434, filed on an even date herewith by Yu, entitled “A Process for Manufacturing MOS Transistors Having Elevated Source and Drain Regions and a High-K Gate Dielectric.” All of the above patent applications are assigned to the assignee of the present application.
FIELD OF THE INVENTION
The present specification relates to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present application relates to a method of manufacturing integrated circuits having thin film transistors.
BACKGROUND OF THE INVENTION
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing transistor density on ICs has been a principal focus of the microelectronics industry. An ultra-large scale integrated circuit can include over 1 million transistors. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices.
In bulk semiconductor-type devices, transistors, such as, MOSFETs are built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided on the top surface between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (and thickness of the depletion layer below the inversion channel) must be scaled down to achieve superior short channel performance.
According to conventional complimentary metal oxide semiconductor (CMOS) fabrication techniques, the reduction of the depletion layer thickness is realized by a super-steep retrograded well (SSRW) ion implantation process. However, this process is limited by the diffusion of dopant atoms during subsequent thermal processes (e.g., annealing). The ion implantation process can generally only achieve an 80-nanometer or larger body thickness for a transistor. Thus, conventional fabrication techniques for bulk semiconductor type-devices cannot create transistors with a body thickness less than 80 nm.
Accordingly, bulk semiconductor-type devices can be subject to disadvantageous properties due to the relatively large body thicknesses. These disadvantageous properties include less than ideal sub-threshold voltage rolloff, short channel effects, and drain induced barrier lowering. Further still, bulk semiconductor-type devices can be subject to further disadvantageous properties such as high junction capacitance, ineffective isolation, and low saturation current. These properties are accentuated as transistors become smaller and transistor density increases on ICs.
The ULSI circuit can include CMOS field effect transistors (FETS) which have semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The source and drain regions are often silicided to reduce source/drain series resistance or contact resistance. However, as body thickness is reduced, the amount of material available for silicidation is reduced. Accordingly, large source/drain series resistance remains a considerable factor adversely affecting device performance.
The source and drain regions can be raised by selective silicon (Si) epitaxy to make connections to source and drain contacts less difficult. The raised source and drain regions provide additional material for contact silicidation processes and thereby reduce deep source/drain junction resistance and source/drain series resistance. However, the epitaxy process that forms the raised source and drain regions generally requires high temperatures exceeding 1000° C. (e.g., 1100-1200° C.). These high temperatures increase the thermal budget of the process and can adversely affect the formation of steep retrograde well regions and ultra shallow source/drain extensions.
The high temperatures, often referred to as a high thermal budget, can produce significant thermal diffusion which can cause shorts between the source and drain region (between the source/drain extensions). The potential for shorting between the source and drain region increases as gate lengths decrease.
Conventional SOI-type devices include an insulative substrate attached to a thin film semiconductor substrate which contains transistors similar to the MOSFET described with respect to bulk semiconductor-type devices. The transistors have superior performance characteristics due to the thin film nature of the semiconductor substrate and the insulative properties of the insulative substrate (e.g., the floating body effect). The superior performance is manifested in superior short channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current.
As transistors become smaller, the thin film semiconductor substrate also becomes thinner. The thinness of the thin film semiconductor substrate prevents effective silicidation on the thin film semiconductor substrate. Effective silicidation is necessary to form source and drain contacts. Without effective silicidation, the transistor can have large source/drain series resistances.
Typically, silicidation must consume a certain volume of the semiconductor substrate (e.g., silicon), which is not abundantly available on the thin film semiconductor substrate. The significant volume of the substrate must be consumed to appropriately make electrical contact to the source and drain regions. Accordingly, SOI-type devices are susceptible to the high series source/drain resistance which can degrade transistor saturation current and hence, the speed of the transistor. The high series resistance associated with conventional SOI CMOS technology is a major obstacle which prevents SOI technology from becoming a mainstream IC technology.
Thus, there is a need for a method of manufacturing thin film, fully depleted MOSFET ICs which has advantages over conventional bulk type devices. Further still, there is a need for a method of manufacturing a transistor which has superior short-channel performance, near

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