Etching a substrate: processes – Nongaseous phase etching of substrate – Using film of etchant between a stationary surface and a...
Reexamination Certificate
2002-06-18
2004-09-21
Goudreau, George A. (Department: 1763)
Etching a substrate: processes
Nongaseous phase etching of substrate
Using film of etchant between a stationary surface and a...
C438S692000, C451S057000
Reexamination Certificate
active
06793837
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a process for material-removing machining of both sides simultaneously of semiconductor wafers using optimized path curves of the semiconductor wafers relative to the upper and lower machining disk.
2. The Prior Art
A typical process sequence for the production of semiconductor wafers comprises the process steps of sawing—edge rounding—lapping or grinding—wet-chemical etching—polishing, as well as cleaning steps before and/or after at least some of the process steps mentioned. Particularly for semiconductor wafers which are to be used as the starting product for the fabrication of modern component generations, for example there are line width requirements of 0.13 &mgr;m or 0.10 &mgr;m. High demands are imposed on the plane parallelism and flatness of the wafers, which in the cases mentioned above can be expressed by the flatness measure SFQR
max
less than or equal to 0.13 &mgr;m or 0.10 &mgr;m for a component surface area of, for example, 25 mm×25 mm. This requirement can be taken into account by at least one manufacturing step in the process sequence being carried out as a step which simultaneously machines the front surface and the back surface of the semiconductor wafers. Examples of such processes include double-side lapping, double-side grinding and double-side polishing, which can be carried out as a single-wafer process or with approximately 5 to 30 semiconductor wafers being machined simultaneously.
The technology of double-side lapping of a plurality of semiconductor wafers simultaneously has long been known and is described, for example, in EP 547 894 A1, and suitable installations are commercially available in various sizes from a number of manufacturers. The semiconductor wafers are moved under a certain pressure and as a result semiconductor material is removed, while a suspension containing abrasives is supplied, between an upper and a lower working disk. This is known by the person skilled in the art as a lapping wheel which generally consists of steel and is provided with channels for improved distribution of the suspension. The wafers are kept on a geometric path by carriers which are set in rotation by means of drive rings and have cutouts for receiving the semiconductor wafers.
The purpose of the lapping is to remove damage which has been produced during the sawing of the semiconductor crystal and to produce a predetermined thickness and plane-parallelism of the semiconductor wafers. Typically, from 20 &mgr;m to 120 &mgr;m of semiconductor material is removed, with this material preferably being divided evenly between the two sides of the semiconductor wafer.
Processes for the double-side grinding of semiconductor wafers are also known and have recently started to replace lapping to a greater extent, on account of cost benefits. In this context, by way of example DE 196 26 396 A1 describes a process which simultaneously machines a plurality of semiconductor wafers and operates with movements of the semiconductor wafer which are similar to those used in double-side lapping. The purpose of the double-side grinding is similar to that of the lapping; the typical amounts of material removed are also similar.
The process of double-side polishing of semiconductor wafers represents a refinement of the lapping process, with planar polishing plates, to which a polishing cloth is attached. They replace the upper and lower lapping wheels as working disks, and with a polishing suspension which generally contains alkali-stabilized colloids being supplied. According to U.S. Pat. No. 5,855,735, at a solids concentration of over 6% by weight there is a transition from the chemical-mechanical double-side polishing to a double-side rough polishing in lapping mode.
Once again, in this case the semiconductor wafers are moved along a fixed path by carriers which are set in rotation, with the upper and lower polishing plates generally rotating in opposite directions. A polishing machine for this purpose is described, for example, in DE 100 07 390 A1. A process for the double-side polishing of semiconductor wafers in order to achieve high degrees of flatness, with the finished polished semiconductor wafers being only 2 to 20 &mgr;m thicker than the carriers made from stainless steel, is known from DE 199 05 737 C2. With this process, it is possible to achieve semiconductor wafers with local flatness values, expressed as SFQR
max
for a grid with component surface areas of 25 mm×25 mm, of less than or equal to 0.13 &mgr;m. This is required for semiconductor component processes with line widths of less than or equal to 0.13 &mgr;m. A process for remachining by double-side polishing is described in DE 199 56 250 C1. To protect the edge of the semiconductor wafers, according to an embodiment described in EP 208 315 B1, the carriers expediently have plastic-lined cutouts for receiving the semiconductor wafers, a process which is also in widespread use in lapping.
The purposes of the double-side polishing are to establish the final plane-parallelism and flatness of the semiconductor wafer and to eliminate damaged crystal layers and surface roughness resulting from the preceding processes, for example lapping or grinding followed by etching. The high flatness of double-side polished semiconductor wafers, combined with the presence of a polished back surface with a reduced tendency to particle adhesion, has led to the following. This abrasive polishing process is of considerably greater importance than single-side polishing of the front surface in particular for the production of semiconductor wafers with a diameter of 200 mm and above. Typically, from 10 &mgr;m to 50 &mgr;m of semiconductor material is removed.
In double-side polishing, generally the same amount of material is removed from the front surface and the back surface of the semiconductor wafers. By contrast, WO 00/36637 claims a process for deliberately leaving damaged crystal layers on the back surface of the wafer by removing increased amounts of material from the front surface during double-side polishing. This can be achieved by using an increased rotational speed of the upper polishing plate. According to DE 197 04 546 A1, asymmetric removal of material of this nature can also be achieved by a multistage process involving double-side polishing—coating of the back surface, for example with oxide—further double-side polishing.
To remain competitive as a manufacturer of semiconductor wafers, it is imperative to provide methods and processes which allow manufacturing with the required quality at costs which are as low as possible. An important approach in this context is to increase the yield of semiconductor wafers per machine to the highest possible level. In the case of double-side polishing, this means, for example, producing high removal rates combined with a high service life of the polishing cloths. The same is also true of double-side lapping and grinding processes, but in this case the service life of the polishing cloths is replaced, for the working disks, by the service life of the lapping wheels or of the abrasive bodies.
A drawback of this process according to the prior art is that with double-side lapping, grinding or polishing, it is impossible, while maintaining certain product properties, for example a high flatness and/or the absence of surface scratches, to achieve an increased machine throughput or a shortened cycle time with a fixed amount of material being removed. Attempts to increase the rate at which semiconductor material is removed by increasing the machining pressure have lead to a deterioration in the flatness and/or to the occurrence of surface scratches. This causes the result that the wafers produced in this way cannot be processed further, but rather have to be discarded or remachined at high cost.
U.S. Pat. No. 6,180,423 B1 describes that, in the case of single-side polishing of only one semiconductor wafer, which is held by a support and is moved in rotation about its center by means of a polishing pl
Altmann Thomas
Heier Gerhard
Kann Gunther
Wenski Guido
Winkler Wolfgang
Collard & Roe P.C.
Goudreau George A.
Siltronic AG
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