DRAM controller with background refresh

Details DRAM controller with background refresh DRAM controller with background refresh

1997-07-29

1998-10-13

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365227, G11C 700

Patent

active

058222650

ABSTRACT:
A DRAM controller refreshers a DRAM having a maximum refresh interval. The DRAM controller measures a time interval after a refresh cycle, monitors a memory request input of the DRAM for an idle period after a measured time interval of substantially less than the maximum refresh interval, and refreshes the DRAM with a refresh cycle upon detecting one of an idle period and a measured time interval of the maximum refresh interval.

REFERENCES:
patent: 5321661 (1994-06-01), Iwakiri et al.
patent: 5418920 (1995-05-01), Kuddes
patent: 5495452 (1996-02-01), Cha
patent: 5617551 (1997-04-01), Corder
patent: 5619468 (1997-04-01), Ghosh et al.
patent: 5682498 (1997-10-01), Harness
patent: 5684751 (1997-11-01), Manning
Circuit Description--H6-41E030-A, ECM 11, 91-E03000-A, Enhanced Common Memory II Card Rockwell Switching Systems Division, Rockwell International--Internal Publication, Mar. 11, 1996 (2 pages).
Circuit Description--Bus Maintenance Unity (BMU)--Rockwell Switching Systems Division, Rockwell International--Internal Publication, Sep. 2, 1992 (2 pages).
Circuit Description--Peripheral Data Interface (PDI) Card--Rockwell Switching Systems Division, Rockwell Internaitonal--Internal Publication, Jul. 31, 1992 (2 pages).

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