Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-19
2004-03-23
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S730000
Reexamination Certificate
active
06711708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a boundary-scan test method and device-for running self-diagnostics on wiring and logic circuits in a semiconductor integrated circuit.
2. Description of the Prior Art
In recent years, a boundary-scan test method that complies with IEEE 1149.1 standard, which is known as Joint Test Action Group (JTAG), has been widely used as a method of running self-diagnostics on wiring and logic circuits in a semiconductor integrated circuit. Referring now to
FIG. 6
, there is illustrated a block diagram showing the structure of a semiconductor integrated circuit into which a boundary-scan test device using such a prior art boundary-scan test method is incorporated. In the figure, reference numeral
1
denotes an internal system logic,
2
denotes an input pin,
3
denotes an output pin,
6
denotes a test data input pin, which will be abbreviated as TDI,
7
denotes a test data output pin, which will be abbreviated as TDO,
8
denotes a test clock pin, which will be abbreviated as TCK,
9
denotes a test mode select pin, which will be abbreviated as TMS,
10
denotes a boundary-scan register chain,
11
a
denotes an input boundary-scan register which partially constitutes an input boundary portion of the boundary-scan register chain
10
,
11
b
denotes an output boundary-scan register which partially constitutes an output boundary portion of the boundary-scan register chain
10
, and
22
denotes a test access port controller, which will be abbreviated as TAPC.
Referring next to
FIG. 7
, there is illustrated a schematic circuit diagram showing the structure of each of the plurality of input boundary-scan registers
11
a
and output boundary-scan registers
11
b
as shown in FIG.
6
. In
FIG. 7
, reference numeral
12
denotes an input multiplexer,
13
denotes a shift register stage,
14
denotes a parallel output stage,
15
denotes a data input signal,
16
denotes a shift data register signal,
17
denotes a clock data register signal,
18
denotes a update data register signal, and
19
denotes a data output signal.
In operation, each of the plurality of input boundary-scan registers
11
a
and output boundary-scan registers
11
b
, which are provided for the plurality of external input and output ports of the semiconductor integrated circuit as shown in
FIG. 6
, can perform either one of basic operations such as capturing, shifting, and updating, according to a transition in the state of the TAPC
22
. In response to a test mode select signal applied to the TMS
9
, the TAPC
22
makes a transition in its state and then applies a control signal having a value set according to its new state to a specified input or output boundary-scan register
11
a
or
11
b
. As a result, the specified input or output boundary-scan register
11
a
or
11
b
performs either one of the following basic operations according to the control signal applied thereto from the TAPC
22
.
(1) Capture Operation
The input or output boundary-scan register
11
a
or
11
b
, which has been specified by a current instruction, captures a signal value from the internal system logic
1
and stores it into the shift register stage
13
thereof.
(2) Shift Operation (Scan Operation)
The input or output boundary-scan register
11
a
or
11
b
, which has been specified by a current instruction, performs scanning. When an input or output boundary-scan register
11
a
or
11
b
is specified by a current instruction, the boundary-scan register chain
10
is connected between the TDI
6
and the TDO
7
and the value of one bit of the specified input or output boundary-scan register
11
a
or
11
b
is shifted by one boundary-scan register towards the TDO
7
in synchronization with a test clock applied to the TCK
8
.
(3) Update Operation
The input or output boundary-scan register
11
a
or
11
b
, which has been specified by a current instruction, updates the content of its parallel output stage
14
. When an input or output boundary-scan register
11
a
or
11
b
is specified by a current instruction, data is then transferred from the shift register stage
13
of the specified input or output boundary-scan register
11
a
or
11
b
to the parallel output stage
14
in synchronization with the test clock applied to the TCK
8
.
When the prior art boundary-scan test device as shown in
FIG. 6
performs scanning, it needs to cause data to be passed through boundary-scan registers other than the boundary-scan register to which data is to be written or from which data is to be read. To overcome the drawback of the prior art boundary-scan test device, Japanese Patent Application Publication (KOKAI) No. 10-19983 discloses an improvement in the prior art boundary-scan test method, in which when writing data, by way of the TDI
6
, into the plurality of input boundary scan registers
11
a
, for example, the plurality of output boundary-scan registers
11
b
are bypassed and the data is then written into only the plurality of input boundary-scan registers
11
a.
A problem with the prior art boundary-scan test device of
FIG. 6
constructed as above is that since the length of the boundary-scan register chain
10
that consists of the plurality of input and output boundary-scan registers
11
a
and
11
b
, i.e., the number of the plurality of boundary-scan registers is fixed, when assembling the semiconductor integrated circuit including the boundary-scan register chain
10
including the predetermined number of input and output boundary-scan registers
11
a
and
11
b
in a package having a lower number of input/output pins, there can exist one or more boundary-scan registers with no corresponding external input/output pin connected thereto, i.e., one or more boundary-scan registers that are invisible from outside the chip. The time required for scanning test is thus increased because of such extra boundary-scan registers. Furthermore, in the above case, it is difficult to use an automatic test pattern generating tool.
The above-mentioned improvement in the prior art boundary-scan test method as disclosed in Japanese Patent Application Publication (KOKAI) NO. 10-19983 cannot solve the above problem that arises when assembling the semiconductor integrated circuit in a package having a lower number of input/output pins, because it bypasses all of the plurality of output or input boundary-scan registers
11
a
or
11
b
at a time.
SUMMARY OF THE INVENTION
The present invention is made to overcome the above problem. It is therefore an object of the present invention to provide a boundary-scan test method and device, capable of changing the length of a boundary-scan register chain comprised of a plurality of boundary-scan registers according to the number of external input/output pins formed on a package in which the semiconductor integrated circuit is assembled.
In accordance with one aspect of the present invention, there is provided a boundary-scan test method of boundary-scan testing a semiconductor integrated circuit using a boundary-scan register chain, comprising the step of: changing the length of the boundary-scan register chain by bypassing one or more predetermined boundary-scan registers included in the boundary-scan register chain according to a bypass control signal applied.
In accordance with a preferred embodiment of the present invention, the boundary-scan test method further comprises the step of, when bypassing a boundary-scan register provided for an input port in a case that a package in which the semiconductor integrated circuit is assembled does not have one corresponding external input pin associated with the boundary-scan register, preventing the input port from floating.
In accordance with another aspect of the present invention, there is provided a boundary-scan test device which can be incorporated into a semiconductor integrated circuit for running self-diagnostics on the semiconductor integrated circuit, the device comprising: a boundary-scan register chain including a plurality of boundary-scan registers connected in s
Burns Doane , Swecker, Mathis LLP
De'cady Albert
Mitsubishi Denki & Kabushiki Kaisha
Torres Joseph D.
LandOfFree
Boundary-scan test method and device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Boundary-scan test method and device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Boundary-scan test method and device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3200862