Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2002-04-30
2004-03-02
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
Reexamination Certificate
active
06699799
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a semiconductor device. More particularly, the present invention relates to a method of forming a semiconductor device used for curing a spin-on-glass (SOG) layer.
2. Description of the Related Art
As device sizes become smaller and integration density increases, patterns formed on a semiconductor substrate become increasingly narrow, while thickness of layers remains constant. For example, a shallow trench isolation (STI) process requires that a width of a device isolation layer be reduced while a depth of the device isolation layer remains unchanged, thereby causing an aspect ratio of a trench to increase. If a contact plug or a via hole is formed, a deep contact hole is formed in a narrow region. As a contact hole formed at an interlayer insulating film becomes narrower, the aspect ratio of the contact hole becomes increasingly higher. Stacking a material layer on a semiconductor substrate having a high step difference often fills a narrow space. In this case, polysilicon or tungsten layers formed by a chemical vapor deposition (CVD) technique have an excellent gap-filling property, but silicon oxide has a relatively poor gap-filling property. Thus, a layer of silicon oxide may cause problems due to the poor gap-filling property of the silicon oxide.
In order to overcome the above-mentioned gap-filling problems, various methods using ozone tetra-ethyl-ortho silicate (TEOS), undoped silicate glass (USG) or high-density plasma chemical vapor deposition (HDP-CVD) have been proposed. Unfortunately, in many cases employing these methods, even stacking oxide layers of HDP-CVD is not sufficient to fill a trench having an aspect ratio of, for example, 5. Therefore, a method using a spin-on-glass (SOG) type oxide layer has been proposed as an alternative.
Since SOG is deposited on a semiconductor substrate using a coating method and is originally liquid-phase or sol-phase, it may have an excellent gap-filling property and efficiently reduce a step difference on a semiconductor substrate. Conventionally, SOG layers have been mainly used as auxiliary layers for planarizing a semiconductor substrate and have not been regarded as suitable for forming semiconductor devices. Recently, various materials and methods for densifying a structure of an SOG layer have been studied and developed, which may contribute to the usefulness of an SOG layer as a gap-filler.
A hydro silsesquioxane (HSQ) layer will now be described as an example of an SOG layer. A liquid-phase HSQ layer is coated on a semiconductor substrate. The coated HSQ layer is subjected to a soft bake process at a temperature of from approximately 100° C. to 300° C. to eliminate a solvent, such as dialkyl ether. The soft-baked HSQ layer is subjected to a hard bake process for dozens of minutes to be hardened. Even though the hard bake process is carried out in an oxidation ambient, the HSQ layer is not fully cured. Curing occurs when an element, other than oxygen or silicon, is replaced with oxygen, thereby forming an oxidized silicon layer. Unlike an HSQ layer filling a trench having a low aspect ratio, very little of an HSQ layer formed in a narrow and deep gap having a high aspect ratio, such as between patterns on a semiconductor substrate, is changed to an oxide layer during the hard bake process.
If the HSQ layer is not fully cured, hydrogen elements remaining in the HSQ cause the HSQ layer to be porous. When the porous HSQ is subjected to an etch (particularly a wet etch) process and a cleaning process, the amount the HSQ layer is etched rises significantly. Therefore, reliability of the etching and cleaning processes performed for the exposed HSQ layer is considerably degraded. If, for example, a contact hole is being formed in the HSQ layer, the degraded etching and cleaning performance causes a bottom of the contact hole to be insufficiently cleaned to secure an adjacent HSQ layer. Thus, contact resistance is increased. On the other hand, if the bottom of the contact hole is sufficiently cleaned, an interlayer insulating film between conductors becomes thin, thereby increasing a parasitic capacitance. If a trench isolation layer is made of HSQ, the trench isolation layer is significantly recessed during processes such as cleaning. As a result, a junction leakage current and an inferior gate oxide layer occur.
Furthermore, because the HSQ layer contracts considerably during a bake process or other similar process, and because a degree of curing is not uniform throughout the HSQ layer, a stress difference occurs from thermal extension. As a result of this stress difference, the likelihood of developing defects such as cracks in the HSQ layer rises, and device reliability deteriorates.
SUMMARY OF THE INVENTION
A feature of an embodiment of the present invention provides a method of forming a semiconductor device that may easily fill an insulating layer on a semiconductor substrate having a high aspect ratio.
Another feature of an embodiment of the present invention provides a method of forming a semiconductor device that may prevent a layer damaged in a wet etch process from having an adverse effect on device characteristics during formation of a silicon oxide layer on a semiconductor substrate using an SOG technique.
Still another feature of an embodiment of the present invention provides a method of forming a semiconductor device that may easily cure an SOG layer into a silicon oxide layer.
A method according to an embodiment of the present invention may be generally summarized as conformally stacking a liner on a semiconductor substrate having at least one concave region, coating a spin-on-glass (SOG) layer on the liner to fill the at least one concave region, and curing the SOG layer.
According to an embodiment of the present invention, curing of the SOG layer may be performed in a high-temperature vapor ambient of from approximately 700° C. to 1000° C. Preferably, the curing is performed in a processing space where oxygen or oxygen radicals exist. As a method for forming these oxygen radicals, a method of irradiating ultraviolet light in an ozone ambient, a method of forming and applying oxygen plasma, and a method of introducing oxygen and hydrogen at a high temperature of 1000° C. may be used. In the event that oxygen and hydrogen are provided at a high temperature, they react with each other to make a high temperature water vapor ambient and enable the oxygen radicals to promote the SOG curing.
The liner may include silicon, silicon nitride or a combination thereof. Here, silicon may include polysilicon, amorphous silicon, conductive impurity doped silicon, germanium doped silicon, or pure silicon. An oxygen barrier layer, such as a silicon nitride layer, may be stacked to form a combination layer before stacking the silicon layer in order to prevent diffusion of oxygen into a lower structure during a high-temperature curing process. During the curing process, the liner is oxidized to be an oxygen flow passage, which helps cure an SOG layer in a deep gap.
The SOG layer may be formed of a conventional HSQ layer. Preferably, the SOG layer is made of a polysilazane-based material that is suitable for a high-temperature curing process and that has an enhanced degree of transformation into an oxide layer. After coating the SOG layer, a chemical mechanical polishing (CMP) process may be performed before or after the curing process. A wet process, such as a wet etch or a cleaning process, is preferably performed after stacking and curing the SOG layer.
These and other features and advantages of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
REFERENCES:
patent: 5858869 (1999-01-01), Chen et al.
patent: 6074939 (2000-06-01), Watanabe
patent: 2001/0005627 (2001-06-01), Matsubara
patent: 8-306681 (1996-11-01), None
Ahn Dong-Ho
Hong Soo-Jin
Lee Jung-Il
Park Kyung-won
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
Thompson Craig
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