Stacked MIMCap between Cu dual damascene levels

Details Stacked MIMCap between Cu dual damascene levels Stacked MIMCap between Cu dual damascene levels

2001-06-01

2004-01-13

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000

Reexamination Certificate

active

06677635

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a stacked metal-insulator-metal (MIM) capacitor in between Cu dual-damascene levels having greater chip area and wherein the thickness of the MIM capacitor dielectric is relaxed and therefore improved in yield, and a method of fabricating said semiconductor device.
2. Description of the Related Art
As semiconductor devices continue to be reduced to smaller and smaller dimensions, capacitors used in integrated circuits such as those in DRAM storage cells, need higher capacitance/unit area.
One manner of accomplishing this is to change from conventional polysilicon-insulator-polysilicon capacitors to metal-insulator-metal (MIM) capacitors.
In the MIM capacitors, metals used as the top and/or bottom electrodes are those with low oxygen affinity. On the other hand, the insulator is generally a metal oxide using metals that have a high oxygen affinity. However, due to their low oxidation resistance, these electrodes are easily oxidized in the O
2
ambient at the high temperatures required during fabrication. This oxidation results in reduced capacitance due to leakage in the device.
More specifically, the metal-insulator-metal capacitor (MIMCap) is a specific type of capacitor having two metal plates sandwiched around a capacitor dielectric, that is parallel to a semiconductor wafer surface. This type of metal-insulator-metal capacitor has been used in mixed mode signal processing and system-on-a-chip applications. For these type of applications, the MIMCap is built in back-end-of-line (BEOL) interconnect levels having a bottom and top metal plate that sandwiches a dielectric layer in between.
A method of fabricating a capacitance structure is disclosed in U.S. Pat. No. 6,177,305 B1. The method comprises:
forming a first electrode layer comprising titanium nitride on a wafer wherein the first electrode is formed in a chemical vapor deposition chamber;
forming an insulating layer on the first electrode layer in the CVD chamber wherein the insulating layer comprises a material selected from the group consisting of titanium oxynitride and titanium oxycarbonitride; and
forming a second electrode layer comprising titanium nitride on the insulating layer, wherein the second electrode layer is formed in the CVD chamber.
A method for fabricating a capacitor in an integrated circuit is disclosed in U.S. Pat. No. 6,156,600. The method comprises:
forming a bottom electrode on a substrate;
forming a first tantalum oxide layer on the bottom electrode;
forming a first tantalum oxide nitride layer on the first tantalum oxide layer;
forming a second tantalum oxide layer on the first tantalum oxide nitride layer; and
forming a top electrode.
U.S. Pat. No. 6,146,941 disclose a method of fabricating a capacitor comprising:
providing a substrate, wherein at least a gate and at least a source/drain region is formed on the substrate, and wherein a spacer is formed at a periphery of the gate and a cap layer is formed at a top of the gate;
forming an insulating layer over the substrate to at least cover the gate and the source/drain region;
patterning the insulating layer to form an opening which exposes the source/drain region, wherein the opening has a side wall;
forming a conformal glue/barrier layer on the side wall and coupled to the source/drain region;
forming a first conformal thin conductive layer on the glue/barrier layer to act as a lower electrode;
forming a dielectric thin film on the first conductive layer; and
forming a second conductive layer on the dielectric thin film to act as an upper electrode.
U.S. Pat. No. 6,144,051 disclose a semiconductor device having a metal-insulator-metal-capacitor. The device comprises:
a substrate;
a metal-insulator-metal (MIM) capacitor disposed over said substrate, the MIM capacitor having a bottom electrode, a high permittivity layer, and a top electrode;
a first dielectric film at least partially covering said MIM capacitor and having an edge protruding from an edge of the bottom electrode;
a second dielectric film disposed on the first dielectric film, the second dielectric film being made from a different material than the first dielectric film;
a first opening formed in the first and second dielectric films that exposes a portion of said top electrode; and
a second opening formed in the first and second dielectric films that exposes a portion of the bottom electrode.
A method for forming a capacitor in which the bottom plate and dielectric layer of the capacitor are formed before the metal interconnect is formed is disclosed in U.S. Pat. No. 6,197,650 B1. As such, thermal treatment of the dielectric layer does not affect the metal interconnect, and the conventional fault that the quality of the dielectric layer is degraded by scant annealing is avoided, and the dielectric layer and metal interconnect can be optimized.
In this method of forming a capacitor and interconnect, the material comprising the second metal layer may comprise Al and Cu.
U.S. Pat. No. 6,180,976 B1 disclose a device including a thin-film capacitor formed on a surface of a substrate. The device comprises:
a first insulating layer having a base plate of the capacitor and a first conductive feature formed entirely within said first insulating layer;
a second insulating material having a top plate of the capacitor and a second conductive feature formed therein, wherein said second conductive feature is in electrical contact with said base plate; and
a dielectric material interposed between said base and top plates, wherein said dielectric material covers at least a portion of said bottom plate.
An MIMCap was built in copper damascene level using Cu as a bottom plate and a metal plate was patterned on top with a silicon nitride as a dielectric in R. Liu et al, “Single Mask Metal-Insulator-Metal (MIM) Capacitor with Copper Damascene metallization for sub-0.18 um mixed mode signal and system-on-a-chip (SoC) applications”, Proc. 2000 IITC, pp111-113 (2000).
However, there is a need in the art of utilizing metal-insulator-metal capacitors (MIMCap) in making semiconductors to be able to increase or double the capacitors capacitance without additional process steps, compared to the existing methods for preparing MIMCap's.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor device comprising a stacked metal-insulator-metal (MIM) capacitor in between Cu dual-damascene levels characterized by greater chip area.
Another object of the present invention is to provide a semiconductor device comprising a stacked metal-insulator-metal (MIM) capacitor in between Cu dual damascene levels characterized by greater chip area and having a thickness of the MIM capacitor dielectric that is relaxed and therefore improved in yield.
A further object of the present invention is to provide a process for preparing a semiconductor device comprising a stacked metal-insulator-metal (MIM) capacitor in between Cu dual-damascene levels so as to increase or double the capacitor's capacitance without utilizing additional process steps, compared to existing methods for preparing MIMCap's.


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R. Liu et al, “Single Mask Metal-Insulator-Metal (MIM) Capacitor with Copper Damascene metallization for sub-0.18um mixed mode signal and system-on-a-chip (SoC) applications”, Proc. 2000 IITC, pp111-113 (2000).

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