Method of improving stability in low k barrier layers

Details Method of improving stability in low k barrier layers Method of improving stability in low k barrier layers

2003-01-13

2004-09-14

Le, D (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S789000, C438S702000, C438S689000, C438S637000, C216S013000, C216S072000

Reexamination Certificate

active

06790788

ABSTRACT:

BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The invention relates to the fabrication of integrated circuits, more specifically to a process for depositing dielectric layers on a substrate, and to the structures formed by the dielectric layer.
2. Description of the Related Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 &mgr;m and even 0.18 &mgr;m feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (dielectric constants of less than 4.0) to also reduce the capacitive coupling between adjacent metal lines. One such low k material is silicon oxycarbide deposited by a chemical vapor deposition process and silicon carbide, both of which may be used as dielectric materials in fabricating damascene features.
One conductive material having a low resistivity is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 &mgr;&OHgr;-cm for copper compared to 3.1 &mgr;&OHgr;-cm for aluminum), a higher current and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, e.g., vias, and horizontal interconnects, e.g., lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed.
However, low k dielectric materials are often porous and susceptible to interlayer diffusion of conductive materials, such as copper, which can result in the formation of short-circuits and device failure. A dielectric barrier layer material is often disposed between the copper material and surrounding the low k material to prevent interlayer diffusion. However, traditional dielectric barrier layer materials, such as silicon nitride, often have high dielectric constants of 7 or greater. The combination of such a high k dielectric material with surrounding low k dielectric materials results in dielectric stacks having a higher than desired dielectric constant.
Therefore, there remains a need for an improved process for depositing dielectric barrier layer materials with low dielectric constants for damascene applications.
SUMMARY OF THE INVENTION
Aspects of the invention generally provide a method for depositing a barrier layer material having a low dielectric constant. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate by introducing a processing gas comprising hydrogen and an oxygen-free organosilicon compound into a processing chamber, wherein the oxygen-free organosilicon compound has the formula SiH
a
(CH
3
)
b
(C
6
H
5
)
c
, wherein a is 0 to 3, b is 0 to 3, and c is 1 to 4, and reacting the processing gas to deposit the barrier layer, wherein the barrier layer has a dielectric constant less than 4 and depositing a first dielectric layer adjacent the barrier layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.
In another aspect, a method is provided for processing a substrate including depositing a barrier layer on the substrate by introducing a processing gas comprising hydrogen and an oxygen-free organosilicon compound into a processing chamber, wherein the oxygen-free organosilicon compound has the formula SiH
a
(CH
3
)
b
(C
6
H
5
)
c
, wherein a is 1 or 2, b is 1 or 2, and c is 1 or 2, and reacting the processing gas to deposit the barrier layer, wherein the barrier layer has a dielectric constant of less than 4, treating the deposited barrier layer to an e-beam curing technique, and depositing a dielectric layer adjacent the barrier layer, wherein the dielectric layer has a dielectric constant less than 4.


REFERENCES:
patent: 3510369 (1970-05-01), Ernick et al.
patent: 4872947 (1989-10-01), Wang et al.
patent: 4895734 (1990-01-01), Yoshida et al.
patent: 4951601 (1990-08-01), Maydan et al.
patent: 5011706 (1991-04-01), Tarhay et al.
patent: 5086014 (1992-02-01), Miyata et al.
patent: 5242530 (1993-09-01), Batey et al.
patent: 5298597 (1994-03-01), You et al.
patent: 5360491 (1994-11-01), Carey et al.
patent: 5465680 (1995-11-01), Loboda
patent: 5468978 (1995-11-01), Dowben
patent: 5480300 (1996-01-01), Okoshi et al.
patent: 6054379 (2000-04-01), Yau et al.
patent: 6147009 (2000-11-01), Grill et al.
patent: 2002/0111042 (2002-08-01), Yau et al.
patent: 2003/0003765 (2003-01-01), Gibson, Jr. et al.
patent: 2003/0003768 (2003-01-01), Cho et al.
patent: 2003/0089988 (2003-05-01), Matsuura
patent: 2003/0111730 (2003-06-01), Takeda et al.
patent: 2003/0129827 (2003-07-01), Lee et al.
patent: 1 107 303 (2001-06-01), None
patent: 09 320 075 (1997-12-01), None
patent: 99/41423 (1999-08-01), None
PCT International Search Report for US/02/36229 dated Sep. 3, 2003 (AMAT/6392.PC).
Ogawa et al., “Novel ARC Optimization Methodology for KrF Excimer Laser Lithography at Low K1 Factor”,Proceedings of the SPIE. Optical/Laser Microlithography V, vol. 1674, 1992, pp. 362-375.
Dijkstra et al., “Optimization of Anti-Reflection Layers for Deep UV Lithography”,Proceedings of SPIE Optical/Laser Microlithography, Bellingham, SPIE, vol. 1927, 1993, pp. 275-286.
Omar, M.A., “Elementary Solid State Physics: Principles and Applications,” Lowell Technological Institute, Addison-Wesley Publishing Company, ® 1975, pp.:124, 125.
PCT International Search Report dated Feb. 11, 2000 for US99/22425. (2966.01 PC).
PCT International Search Report for US02/40034 dated May 19, 2003. (AMAT/6084.PC).
Wu, et al. “Advanced Metal Barrier Free Cu Damascene Interconnects with PECVD Silicon Carbide Barriers for 90/65-nm BEOL Technology”, 2002 IEEE, IEDM pp. 595-598.

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