Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-01-06
2004-05-25
Auduong, Gene (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S321000
Reexamination Certificate
active
06740927
ABSTRACT:
The present invention relates to a semiconductor device, and more specifically, to a method of fabricating nonvolatile memory capable of storing multi-bits binary information and the novel device structure.
BACKGROUND OF THE INVENTION
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated Circuit (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction in the size of a device. The nonvolatile memories include various types of devices. Different types of devices have been developed for specific applications' requirements in each of these segments. Flash memory is one of the segments of nonvolatile memory devices. The device includes a floating gate to storage charges and an element for electrically placing charge in and removing the charges from the floating gate. One of the applications of flash memory is BIOS for computers. Typically, the high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid-state camera and PC cards. It is because that the nonvolatile memories exhibit many advantages, such as memory retention without power, fast access time, low power dissipation in operation, and robustness.
The formation of nonvolatile memories toward the trends of low supply power and fast access, because these requirements are necessary for the application of the mobile computing system. Flash memory needs the charges to be hold in the floating gate for a long period of time. Therefore, the dielectric that is used for insulating the floating gate needs to be high quality in insulation and good durability in writing. At present, the low voltage flash memory is applied with a voltage of about 5V to 10V during charging or discharging the floating gate. As known in the art, the tunneling effect is a basic technology in charging or discharging. In order to attain high tunneling efficiency, the thickness of the dielectric between the floating gate and substrate have to be scaled down due to the supply voltage is reduced. The data program method of a non-volatile memory device includes a method using Fowler-Nordheim (FN) tunneling or a method using hot electron injection. In FN tunneling, a high voltage is applied to a control gate to induce a high electric field in a tunnel oxide layer, and electrons of a semiconductor substrate pass the tunnel oxide layer and are injected into a floating gate. During the mode of erasing, the bias may apply on the source to discharge the electron from the floating gate to the source of a memory device.
Conventional memory cell consists of a source region, a drain region, a floating gate (FG), a control gate (CG) and insulation films. A plurality of sectors are arranged in the two-dimensional manner on a semiconductor substrate of the flash memory. Memory cells are separated from one another by an element isolation region of LOCOS (local oxidization of silicon) or STI (shallow trench isolation). When writing a new data or rewriting a data stored in the flash memory, the stored data in memory cells are erased on the sector basis immediately before the writing. The device is called flash due to the data is erased sector by sector.
The prior art single bit charge trapping dielectric flash EEPROM memory cells are constructed with a charge trapping ONO layer. The memory cell generally includes a P-type silicon substrate and two PN junctions between N+ source and drain regions and P type substrate, a nitride layer sandwiched between two oxide layers and a polycrystalline layer. To program or write the cell, voltages are applied to the drain and the gate and the source is grounded. These voltages generate a vertical and lateral electric field along the length of the channel from the source to the drain. This electric field causes electrons to be drawn off the source and begin accelerating towards the drain. The hot electrons are generated at the boundary between drain and channel during the acceleration. These hot electrons are then redirected vertically into the ONO layer. Two of the ONO memories capable for storing two bits binary can refer to U.S. Pat. No. 6,011,725 to Boaz and U.S. Pat. No. 6,335,554 to Yoshikawa.
To further understand the role of “floating gate”, please refer to
FIG. 1A
, it illustrates the well-known programming of the flash device. During the mode of programming, positive bias is applied on the control gate
105
for tunneling the carriers through the oxide
102
from the source
101
a
of the substrate
101
to the floating gate
103
. In the erasing mode, negative bias, for example, is introduced on the control gate
105
while positive bias is applied on the drain
101
b
to force the electron out of the floating gate to the source, as shown in
FIG. 1
b.
In the prior art, a set of data can be programmed or erased at one time. The number of the memory units in the flash memory means the number of cells that can be programmed or erased. If there exist two sectors to store the data in a single cell, respectively, the device may program or erase two sets of data. Therefore, the capacity of the data set that is programmed or erased by this flash device is twice of the number of the traditional memory units in the flash memory.
SUMMARY OF THE INVENTION
The object of the present invention is to disclose a flash device with multi-bits cell capable of storing multi binary information bits. The further object of the present invention is to provide the method of forming the memory.
A method for manufacturing a nonvolatile memory capable of storing multi-bits binary information is disclosed. The method comprises the steps of forming an oxide on the semiconductor substrate. A conductive layer is formed on the oxide layer. A conductive layer is patterned to form a gate structure to act as a control gate. A first isolation layer is formed over the gate structure. A second isolation layer is formed over the first isolation layer. Then, performing an etching to etch the first isolation layer and the second isolation layer, thereby forming a L-shape structure attached on sidewall of the gate structure and a spacer on the L-shape structure, wherein the spacer functions as floating gate. Subsequently, an ion implantation is performed using the gate structure and the spacer as a mask to form source and drain regions in the semiconductor substrate adjacent to the spacer, wherein a channel under the gate structure keeps a distance from the source and drain regions. This distance connected between channel and drain region (or source region) is known as “fringing field induced channel” which is to be turned on by the gate voltage induced electric fringing field.
A silicide material is further formed on the gate structure and the source and drain regions. The silicide material includes TiSi
2
, CoSi
2
or NiSi. Wherein the spacer is formed by an anisotropical etching and the first isolation layer includes SiO
2
or HfO
2
. The second isolation layer includes nitride.
A nonvolatile memory capable of storing multi-bits binary information bits is provided. The memory includes an oxide formed on a substrate. A control gate is formed on the oxide. A L-shape structure is attached on sidewall of the control gate. Spacers are formed on the L-shape structure to act as a floating gate. A first doped region and a second doped region is formed in the substrate adjacent to the spacers. Wherein the spacers represent a first binary status by injecting and storing electrical charge in the spacers or to represent a second binary status by not injecting electrical charge into the spacer. A first and a second fringing field induced channels are under the first and the second spacers, wherein the first and the second fringing field induced channels are located between the main gate-induced channel. The first and the second doped regions sit adjacent to the first and the second fringing field induced channels, respectively. The main gate-induced channel is referred to the channel generated under the gate by conventional fashion. The fringing f
Applied Intellectual Properties Co., Ltd.
Auduong Gene
Perkins Coie LLP
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