Semiconductor memory device and data read method thereof

Details Semiconductor memory device and data read method thereof Semiconductor memory device and data read method thereof

2002-02-13

2004-04-13

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S207000, C365S202000, C327S051000, C327S052000

Reexamination Certificate

active

06721218

ABSTRACT:

CROSS REFERENCE TO OTHER APPLICATIONS
This application claims the benefit of Korean Patent Application No. 2001-9340, filed on Feb. 23, 2001, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a data read method of the semiconductor memory device.
2. Description of Related Art
In a typical semiconductor memory device, different memory cells have different path lengths to a current sense amplifier. The different path lengths result in a difference of the speed of reading. At its worst, the difference is the largest between data read from memory cell farthest from the current sense amplifier and data read from the memory cell nearest to the current sense amplifier.
FIG. 1
is a block diagram illustrating a conventional semiconductor memory device. The semiconductor memory device includes a plurality of memory cell arrays
10
-
1
to
10
-
8
. Each of the memory cell arrays
10
-
1
to
10
-
8
includes a plurality of memory cells MC
1
and MC
1
B to MC
4
and MC
4
B near a crossing point of a plurality of word lines WL
1
to WLm and a plurality of bit line pairs BL
1
P to BL
4
P.
The bit line pairs BL
1
P to BL
4
P are connected to sense amplifiers
12
-
1
to
12
-
4
, data IO gates IOG
1
to IOG
4
, bit line isolation gates ISG
1
to ISG
4
, and pre-charge circuits PRE
1
to PRE
4
, respectively.
Each of the data IO gates IOG
1
to IOG
4
includes NMOS transistors N
1
and N
2
. Each of the bit line isolation gates ISG
1
to ISG
4
includes NMOS transistors N
3
and N
4
. Each of the pre-charge circuits PRE
1
to PRE
4
includes NMOS transistors N
5
and N
6
.
A column decoder
18
decodes a column address CA to generate column selecting signals Y
0
to Yn.
Each of local data IO line pairs LIO
1
P to LIO
8
P is arranged between the two adjacent memory cell array blocks, and current sense amplifier load circuits
14
-
1
to
14
-
9
are connected to the local data IO line pairs LIO
1
P to LIO
8
P, respectively.
The local data IO line pairs LIO
12
P and LIO
78
P are line pairs shared between the adjacent two memory cell array blocks. The local data IO line pairs LIO
1
P and LIO
78
P are connected to a data IO line pair DIO
1
P, and the local data IO line pairs LIO
12
P and LIO
8
P are connected to a data IO line pair DIO
2
P. The data IO line pairs DIO
1
P and DIO
2
P are connected to the current sense amplifiers
16
-
1
and
16
-
2
, respectively.
Of all the cells in the array,
FIG. 1
only shows the memory cells MC
1
and MC
1
B, and MC
2
and MC
2
B that are the farthest from the current sense amplifier
16
-
1
and
16
-
2
, and also the memory cells MC
3
and MC
3
B, and MC
4
and MC
4
B that are the nearest to the current sense amplifier
16
-
1
and
16
-
2
. It also shows a circuit configuration to input into and output from the memory cells MC
1
and MC
1
B to MC
4
and MC
4
B.
In
FIG. 1
, “SA” denotes a bit line sense amplifier, “CSAL” denotes a current sense amplifier load circuit, and “CSA” denotes a current sense amplifier.
A read operation of the semiconductor memory device of
FIG. 1
is as follows: a pre-charge signal PRE is applied to pre-charge the bit line pairs BL
1
P to BL
4
P. An active command and a row address (not shown) are applied, so that the word line WL
1
is enabled. When a bit line isolation signal ISO
1
having a logic “high” level is generated, a data transmission is performed between the memory cells MC
1
and MC
1
B, and MC
2
and MC
2
B that are connected to the word line WL
1
and the bit line pairs BL
1
P and BL
2
P. The bit line sense amplifiers
12
-
1
and
12
-
2
amplifies data of the bit line pairs BL
1
P and BL
2
P.
When a read command (not shown) and a column address CA is applied, the column decoder
18
generates the column selecting signal Y
0
having a logic “high” level. So the data IO gates IOG
1
and IOG
2
are turned on to transfer data of the bit line pairs BL
1
P and BL
2
P to the local data IO line pairs LIO
1
P and LIO
12
P. The current sense amplifier load circuits
14
-
1
and
14
-
2
supply an electric current for the local data IO line pairs LIO
1
P and LIO
2
P and the data IO line pairs DIO
1
P and DIO
2
P. The current sense amplifiers
16
-
1
and
16
-
2
amplify a current difference between the data IO line pairs DIO
1
P and DIO
2
P to generate data D
1
and D
2
.
In the semiconductor memory device of
FIG. 1
, data read from the memory cells MC
1
and MC
1
B and MC
2
and MC
2
B farthest from the current sense amplifiers
16
-
1
and
16
-
2
and differ in read speed the most from data read from the memory cells MC
3
and MC
3
B and MC
4
and MC
4
B nearest to the current sense amplifier
16
-
1
and
16
-
2
. That is, a transmission speed of data read from the memory cells MC
1
and MC
1
B and MC
2
and MC
2
B farthest from the current sense amplifiers
16
-
1
and
16
-
2
is later than that of data read from the memory cells MC
3
and MC
3
B and MC
4
and MC
4
B nearest to the current sense amplifier
16
-
1
and
16
-
2
. This is because a resistance value between the memory cells MC
1
and MC
1
B and MC
2
and MC
2
B and the current sense amplifiers
16
-
1
and
16
-
2
is larger than the memory cells MC
3
and MC
3
B and MC
4
and MC
4
B and the current sense amplifiers
16
-
1
and
16
-
2
. This is due to the longer path.
FIG. 2
is a simplified circuit diagram illustrating a read operation modeling of the semiconductor memory device of FIG.
1
. In
FIG. 2
, “Icell” denotes a memory cell current, and “Rload” denotes a resistor of a circuit that serves as a load during a data read operation, and “Vin” denotes an input voltage of the current sense amplifier, and “Rin” denotes an input impedance of the current sense amplifier, and “Iin” denotes an input current of the current sense amplifier.
As seen in
FIG. 2
, during a data read operation, the memory cell current Icell dividedly flows to the load resistor Rload and the input impedance Rin of the current sense amplifier.
The input current Iin is described as the following equation:
Iin=Rload
/(
Rload+Rin
)×
Icell
  (Equation 1)
The input voltage is described as the following equation:
Vin=Iin×Rin
  (Equation 2)
If a resistance value of the input impedance Rin of the current sense amplifier becomes very small or “0”, all amount of the memory cell current Icell flows to the current sense amplifier. At this time, a resistance value of the input impedance, a voltage difference of the data IO line pair, becomes very small or “0”.
The resistance value of the input impedance Rin depends on a distance from the current sense amplifier to the memory cell. The larger the distance from the current sense amplifier to the memory cell becomes, the larger the resistance value of the input impedance Rin becomes.
Therefore, the farther the memory cell is from the current sense amplifier, the later a data read speed of the memory cell becomes.
FIG. 3
is a circuit diagram illustrating the current sense amplifier of FIG.
1
. The current sense amplifier includes PMOS transistors P
1
and P
2
and NMOS transistors N
7
to N
9
.
A resistance value for the input impedance of the circuit of
FIG. 3
is obtained as follows. Note that “Iin” denotes an input current that flows through the PMOS transistor P
1
, and “Vin” denotes an input voltage, and “gmp” denotes a mutual conductance between the PMOS transistors P
1
and P
2
, and “gmn” denotes a mutual conductance between the NMOS transistors N
7
and N
8
.
The input current Iin is described as the following equation:
Iin
=(
Vin−Vout
)×
gmp
  (Equation 3)
The output voltage is described as the following equation:
Vout=−
1×(
gmp/gmn
)
2
×Iin
  (Equation 4)
Accordingly, a resistance value of the input impedance Rin is obtained by the following equation:
Rin=Vin/Iin=
1/
gmp×
(1−(
gmp/gmn
)
2
)  (Equation 5)

Affiliated with

Also associated with

Rating

Semiconductor memory device and data read method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device and data read method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and data read method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3193814