Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-09
2004-01-06
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S182000, C438S256000, C438S258000
Reexamination Certificate
active
06673674
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a memory cell with a floating gate, and a method of manufacturing the same.
A conventional, general flash memory will be described with reference to FIG.
4
and
FIGS. 5A and 5B
.
In the memory cell of the flash memory shown in
FIGS. 5A and 5B
, floating gates
503
are formed on a semiconductor substrate
501
through gate insulating films
502
. Each floating gate
503
has a T-shaped section and an upper portion extending horizontally. This shape increases the capacity of the floating gate
503
.
A source
504
and drain
505
are formed on the two sides of the insulating film
502
of the semiconductor substrate
501
, and element regions are defined and isolated by isolation oxide films
506
for element isolation. A control gate
508
is formed on the floating gates
503
through an ONO film
507
. The control gate
508
forms part of a word line. The source
504
and drain
505
are formed in common for the plurality of floating gates
503
, and the commonly formed drain
505
is used as part of a bit line.
As shown in
FIGS. 4 and 5A
, the flash memory has a plurality of memory cells defined by the isolation oxide films
506
in the direction of gate length. The plurality of floating gates
503
are regularly arranged to be spaced apart from each other at predetermined distances in a direction perpendicularly intersecting the direction of gate length, thereby forming a memory cell array comprising the plurality of memory cells. As shown in
FIGS. 4 and 5B
, the common drain
505
used as part of the bit line is connected at the end portion of one memory cell to a bit interconnection
511
through a contact
509
. The bit interconnection
511
is formed on the control gate
508
through an interlevel insulating film
510
.
In the planar arrangement of the flash memory shown in
FIG. 4
, the plurality of control gates
508
are formed to be elongated in the direction of length of the gates, and are arranged in parallel to each other to connect the corresponding memory cell rows of the respective memory cell arrays. The plurality of pairs of source
504
and drain
505
are formed to be elongated in the direction perpendicularly intersecting the gate length, and are arranged in parallel to each other to correspond to the memory cell arrays.
As described above, in the conventional flash memory, the source
504
and drain
505
are formed in common for the plurality of memory cells. The drain
505
is used as part of the bit line, and one contact to be connected to the bit line is arranged for the plurality of memory cells. Therefore, the gaps among the memory cells can be decreased in the direction of gate length, and the cell size can be reduced.
In a flash memory loaded in, e.g., a microcomputer, a higher read speed is required to cope with the microcomputer that operates at a high speed. As described above, in a cell array in which a drain is used in common for a plurality of memory cells and a contact is connected to one portion of the plurality of memory cells, the drain region has a sheet resistance of as high as 100 &OHgr;/□, which becomes a high drain resistance for a memory cell far from the contact, to interfere with the high-speed operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device that can operate at a higher speed, and a method of manufacturing the same.
In order to achieve the above object, according to the present invention, there is provided a semiconductor device having a plurality of memory cells, each of the memory cells comprising a floating gate formed on a semiconductor substrate of a first conductivity type through a gate insulating film to be insulated from a surrounding portion, a control gate formed on the floating gate through an isolation insulating film, a first source and first drain formed on the semiconductor substrate on two sides of the floating gate and doped with an impurity of a second conductivity type, and a first silicide layer formed on a surface of at least one of the first drain and first source.
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“A 1.28&mgr;m2Contactless Memory Cell Technology for a 3V-Only 64Mbit EEPROM,” H. Keme, et al., 1992 IEDM Tech. Dig., pp. 991-993.
“A 0.4-&mgr;m2Self-Aligned Contactless Memory Cell Technology Suitable for 256-Mbit Flash Memories,” M. Kato et al., 1994 IEDM Tech. Dig., pp. 921-923.
Inoue Ken
Sugawara Hiroshi
Ha Nathan W.
NEC Electronics Corporation
Pham Long
Young & Thompson
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