Method of forming an interlayer dielectric film

Details Method of forming an interlayer dielectric film Method of forming an interlayer dielectric film

2002-02-20

2004-07-13

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S758000

Reexamination Certificate

active

06762126

ABSTRACT:

This application claims benefit and priority of Korean Patent Application No. 2001-8859, filed on Feb. 22, 2001, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming an interlayer dielectric film, and more particularly, to a method for coating a wiring pattern using an SOG (spin on glass) solution.
Recently, great strides are being made in the semiconductor technology for information media, and computers. Often, it is desirable for a semiconductor device to operate with high speed and to provide memory of large storing capacities. Accordingly, semiconductor device manufacturers strive to improve levels of integration, reliability and response speed.
Exemplary integrated circuits may include a plurality of active devices that are isolated on a semiconductor substrate. The active devices are typically isolated from each other during the early stages of a semiconductor manufacturing process. Later in the process, the devices may be electrically interconnected to form circuits. Multilevel interconnection structures may serve to interconnect the plurality of devices.
When forming such multilevel interconnection structures, it may become more difficult to keep a smooth topography for a top layer of the interconnection structure as its number of layers increases. For example, when forming a semiconductor wafer with two metal layers, a first interlayer dielectric film may be deposited over the semiconductor wafer. Note, it will be understood that semiconductor substrate may comprise a partially processed device which may include previously fabricated transistors and other electrical circuit elements. Next, vias may be formed in the first dielectrical layer and a second metal layer deposited thereover and coupled to the substrate through the dielectric. If the surface of substrate is uneven, then the surface of the dielectric layer may also be uneven. Accordingly, when forming the second metal layer on the surface of the dielectric, such second metal wiring layer may suffer breaks or fractures resulting from the protrusions or cracks of the lower layer. In other words, because of the uneven surface of the dielectric, the second metal may end up being formed non-uniformly over the dielectric, which in turn may adversely affect a yield of the semiconductor device. To prevent such difficulties, the dielectric may be planarized before forming the vias or second metal wiring layer.
Exemplary planarizations include use of a BPSG (borophosphorous silicate glass) or SOG (spin-on-glass) of superior reflow characteristics, or use of CMP (chemical mechanical polishing) processing of such dielectrics.
BPSG is a common type of dielectric for filling gaps between metal lines. However, the quality of BPSG deposition can depend greatly upon the type and quality of equipment, processes and processing chamber. In addition, the materials and gases for these processes can be very expensive, toxic and hazardous.
Furthermore, as device geometrics drop with increased levels of integration, line spacings similarly decrease. If a bridge defect is formed between conductive lines, it may simply be buried by, e.g., BPSG of an interlayer dielectric film. Thus, the bridges may result in the formation of voids that may hinder etch stop capabilities and in general effect semiconductor-manufacturing yield. Accordingly, there appears to be a need for a processor that may be able to avoid some of the above problems.
Referencing
FIG. 1
, when dielectric
14
is coated on wiring pattern
12
on semiconductor substrate
10
, the surface of dielectric
14
may be uneven. The uneven surface may result from a step or difference in elevation of the upper surface of the substrate relative to the upper surface of lines
12
. To remove the surface protrusions of dielectric
14
, an etch back or CMP process may planarize the surface of dielectric
14
.
As shown in
FIG. 2
, a portion of dielectric
14
is planarized until obtaining a flat surface. Note, wiring pattern
12
is not exposed. For such “partial” CMP process, the density of the metal wring pattern
12
may still affect the degree of planarity and the amount of material that may need to be removed by the CMP process. For example, a dishing effect (a phenomenon that a dish-shaped recess is formed on the polished surface) may occur. To improve the dielectric planarity and reduce the dishing effect, a “full” CMP process, referencing
FIG. 3
, may be performed to polish the dielectric until exposing upper portions of the metal wiring pattern
12
. Accordingly, a separate insulating film e.g., such as an oxide, may be formed to insulate and cover the exposed metal.
As used hereinafter, metal wiring pattern may be referenced alternatively as wiring pattern, metal lines, or simply lines.
For the full CMP process, micro scratches may result. Depending on the kinds of slurries used in the CMP process, undesirable residue may collect in the micro scratches and adversely affect following processes. Some of the adverse effects might even result in a failure of the semiconductor device.
Furthermore, after completing a full CMP process, a surface step may result between an upper surface of lines
12
relative to that of dielectric
14
between the lines. The full CMP process creates the step since the interlayer dielectric film
14
that resides between the lines may be over-polished. As shown in
FIG. 4
, the step, or difference in elevations, may be attributed to a slight over-polishing of dielectric
14
. Again, the step may exert a bad influence upon the capping oxide
16
, in which an unevenness of the surface can affect the planarity of the surface of capping oxide
16
.
In another technique, dielectric film may be formed from a spin-on-glass or SOG process and planarization may be obtained through a coating process. For example, U.S. Pat. No. 5,310,720, issued to Shin et, al, discloses a method for converting a polysilazane layer to silicon oxide by firing the polysilazane in an oxygen atmosphere.
A polysilazane based SOG has Si—N, Si—H and N—H bonds. The N—H bonds are replaced with Si—O bonds when baked in an atmosphere including oxygen and water. Because the method for forming the silicon oxide film using the SOG may be carried out by a simple spin coat and cure process, the method allows reduced manufacturing costs. However, the Si—N bonds may not always be replaced with the Si—O bonds (refer to Japanese Laid-Open Patent Publication No. 11-145286). With residual S-N bonds, the resultant film may have insulating and other electrical features that differ from those of conventional silicon oxide films, such as, e.g., BPSG or TEOS films. In some instances the resultant film with the residual S-N bonds may cause subsequent problems.
U.S. Pat. No. 5,976,618, issued to Shunichi Fukuyama et, al, discloses a method for converting an inorganic SOG film to silicon oxide a through two-step heat treatment processes. Formed by a spin-coating method and of this particular example, the thickness of the silicon oxide film may be insufficient to cover conductive patterns, e.g., such as a gate electrode or a metal line.
With regards to the SOG composition with polysilazane, a pre-baking process may be carried out for a few minutes below 500° C. Then, an annealing process may be provided for tens of minutes at temperatures above 500° C. and in an oxidation atmosphere so as to convert the polysilazane to silicon oxide. But when the SOG film is subject to the anneal, SiH
4
may be released from the film, which in turn may react with an oxidation gas to form SiO
2
contaminates within the process chamber of the anneal. Some of these particles may have a size greater than 10 nm and may cause damage to the wafer that is being annealed within the process chamber.
The oxide obtained at a periphery may be thick. If it exceeds a given thickness, e.g., MCFT (maximum crack free thickness) such as 15,000 A then the oxide may be vulnerable to cracking after the annealing.
SUMMARY OF THE INVENTION

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