Three layer aluminum deposition process for high aspect...

Details Three layer aluminum deposition process for high aspect... Three layer aluminum deposition process for high aspect...

2002-11-27

2004-09-21

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S652000, C438S688000

Reexamination Certificate

active

06794282

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to DRAM fabrication and more particularly, to a process for forming a DRAM by utilizing a three layer aluminum deposition for contact levels (CL) for Al fill for the generation of 70 nm or 90 nm groundrule devices.
2. Description of the Related Art
DRAM devices, such as semiconductor memories, processors, integrated circuits and the like, include layers of contact levels (CL) used to interconnect layers of metal. These conductive or metal lines (ML) are often formed on upper levels of a semiconductor device, and these metal lines are generally connected by contacts through vias to underlying devices or other metal lines.
In the typical method, an Aluminum (Al) metal line deposition includes a two step process, and this process is a cold-hot process. The cold-hot process is extremely slow and has a throughput of only about 22 wafers per hour for a two physical vapor deposition (PVD) Al chamber main frame. The cold-hot process includes two depositions (cold and hot). The first or cold deposition suffers from the disadvantage of running unchucked, meaning that there is no opportunity to check whether the wafer is sitting correctly on the chuck that secures the wafer in a processing chamber.
If the wafer is not placed correctly on the chuck, the chuck may get deposited upon and ruined. This is disadvantageous since an electrostatic chuck is very expensive.
A further problem with the conventional cold-hot process is the heat-up time needed in between the two Al depositions. After the cold Al deposition, the wafer is heated. However, during that time, a thin Al
3
O
2
layer may be formed on the prior deposited Al, and this increases the contact resistance.
The cold-hot process sequence may employ a sprint approach wherein a via has to get filled and concurrently a planar Al film is deposited. The planar Al film is then etched for structuring metal lines.
Requirements for the Al deposition may include the following steps:
a) vias formed in a dielectric (oxide) layer that are tapered to get filled reliably;
b) a planar or low topography Al film is formed on top of the dielectric layer; and
c) a temperature budget for semiconductor processing is maintained (i.e., little or no influence on sub lying metal lines).
Towards this end, a two step Al deposition process was developed.
The two step process begins with a cold step that uses high sputter power and runs at low temperatures to ensure that the vias are getting filled (i.e., small Al grains and no overhangs at the top edge of the vias), and that no voids are formed. Before the second or hot Al deposition step starts, the wafer temperature is increased up to 350° C.
This second Al deposition process runs at low power to ensure that the Al film gets planarized during deposition, however; this Al deposition sequence is not a reflow process.
Reflow processes generally run at much higher temperatures and were developed for filling more aggressive (higher aspect ratio) via structures. Accordingly, the hot Al deposition process has to fulfill different requirements and is optimized for tapered via fill and planar Al deposition on top of a dielectric layer.
The conventional two-step deposition process is very slow due to the relatively long Al deposition time and a small amount of TiAl
3
forms which increases contact resistance and decreases the electromigration lifetime.
In general, in the conventional processes, the actual process of preparing the DRAM, the CL and ML requires an Al fill during a two step PVD process, as already mentioned; however, the first step is a non-chucked PVD to create small grains at the bottom of the CL, and the second step, which is performed at about 350° C. sputters the deposit to the remaining thickness. Nevertheless, this two-step process is inadequate to fulfill the challenges needed due to the increasing aspect ratios that are necessary to make a void-free Al fill.
U.S. Pat. No. 5,807,760 disclose a method of preparing semiconductor integrated circuit fabrications by:
preheating a substrate having partially formed integrated circuits thereon by exposing it to an ambient environment at 150°-200° C.;
commencing the deposition of an aluminum-rich layer, the deposition taking place in an ambient environment at a temperature, t, where 350° C.≦t≦400° C.; the temperature of the substrate gradually increasing during the deposition; and
further including the step of depositing an anti-reflective coating upon the deposited metal, the deposition of anti-reflective coating taking place upon a support structure maintained at a constant temperature.
The deposition of an aluminum nitride comprising layer over a semiconductor substrate in preparing DRAM circuitry is disclosed in U.S. Pat. No. 6,352,944 B1. The process entails:
positioning a semiconductor substrate within a chemical vapor deposition reactor; and feeding ammonia and at least one compound of the formula R
3
Al, where “R” is an alkyl group or a mixture of alkyl groups, to the reactor while the, semiconductor substrate is at a temperature of less than 500° C. and at a reactor pressure from about 100 mTorr to about 725 Torr effective to deposit a layer comprising substantially amorphous aluminum nitride over the semiconductor substrate at the reactor temperature and the reactor pressure.
U.S. Pat. No. 6,136,709 disclose a metal line one step deposition process for semiconductor devices comprising:
providing a semiconductor wafer including a dielectric layer formed on the semiconductor wafer, the dielectric layer having vias formed therein;
placing the semiconductor wafer on a thermal surface in a deposition chamber;
heating the semiconductor wafer to a first temperature by employing the thermal surface;
depositing a metal on the semiconductor wafer to concurrently fill the vias and cover a top surface of the dielectric layer wherein the metal depositing is initiated when the semiconductor wafer is at the first temperature and the metal depositing is continued while heating the semiconductor wafer to a target temperature which is greater than the first temperature; and
controlling an intermediate temperature of the semiconductor wafer between the first temperature and the target temperature by programming a thermal gradient in the thermal surface on which the semiconductor wafer is mounted in the deposition chamber.
There is a need to improve the process of depositing aluminum layers for conductive lines for an Al fill for smaller groundrule devices, wherein the ground rules are about 70 nm or about 90 nm to meet the challenges of the increasing aspect ratios for conductive lines that require a void-free Al fill, and for which the two-step PVD process is inadequate.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a three layer aluminum deposition process for high aspect ratio CL contacts to accommodate increasing aspect ratios for the CL so as to make a void-free Al fill, and thereby satisfy the challenge for the DRAM generation of about 70 nm or about 90 nm ground rules.
A further object of the present invention is to provide a three layer aluminum deposition process for high aspect ratio CL contacts, wherein the process starts with a cold deposition followed by relatively thin 250 nm thick hot layer deposition that is sputtered to provide a reflow on the hot chuck, and following the reflow, a third part of the Al PVD is performed.
In general, the three layer aluminum deposition process for preparing high aspect ratio CL contacts of the invention is accomplished by:
a) introducing a semiconductor wafer into a deposition chamber, said semiconductor comprising a bottom layer of an intermetal dielectric, a target layer intermetal dielectric patterned to form a trench that includes contact holes or vias and/or conductive line openings disposed on said bottom inter metal dielectric, said target layer further including a target conductor or metal layer, said target conductor or metal layer is a substrate having diffusion regions therein or conductive lines fo

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