Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2003-03-21
2004-07-27
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C257S781000, C257S784000, C257S786000
Reexamination Certificate
active
06768207
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a multi-chip module (MCM) package.
2. Description of the Related Art
Due to the configuration of electronic products becoming more and more light and compact, packages protecting semiconductor chips and connecting external circuits are required in a light and compact size.
An electrical package structure generally comprises at least one active device disposed on one circuit substrate. The active device is generally a chip cut from a wafer (made of silicon, germanium arsenide, gallium arsenide). A package comprising one device is generally referred to as a single-chip module (SCM) package, and a package comprising a plurality of devices is generally referred to as a multi-chip module (MCM) package.
With the increasing requirement of minimization and high operating speed for electronic devices, the MCM package, therefore, is becoming more and more popular. The MCM package can combine two or more than two chips together into a single package so as to reduce the limitation of the operating speed of an electronic device. In addition, the MCM package can shorten the connected length between chips so as to reduce signal delay and access time of the electronic device.
FIG. 1
shows a side-by-side MCM package, a conventional MCM package, in which more than two chips
10
′,
11
′, and
12
′ are mounted side by side to a main mounting surface of a common substrate
14
. The connections of wirings (not shown) between the chip and the common substrate are generally completed by wire bonding method. The advantage of such package is that wafers
10
,
11
, and
12
, respectively having high-density devices or chips
10
′,
11
′, and
12
′, are produced with their respective manufacturing processes incompatible to one other; then the devices or chips
10
′,
11
′, and
12
′ are integrated into the common substrate
14
with an arrangement of low-density manner. However, such side-by-side MCM package still has some disadvantages. First, the package efficiency is relatively low since the area of the common substrate needs to increase as the number of chips increase. Secondly, the packaging process of the chips proceeds after the wafer-dicing process and the chip-arranging process, therefore the chips is easily contaminated when compared to a wafer-level package technique.
Therefore, the semiconductor packaging industry has developed chip-stack package. U.S. Pat. No. 5,973,403 discloses a multichip stacked device for stacking a wire-bonded chip on a flip-chip bonded chip as shown in FIG.
2
and FIG.
3
. The multichip stacked device comprises a semiconductor chip
25
disposed on a substrate
20
by a flip-chip bonding method, and a second semiconductor chip
26
stacked on the first semiconductor chip
25
and electrically connected to the substrate
20
by a wire-bonding method. The substrate
20
has a plurality of wire-bonding pads
22
and a plurality of flip-chip bonding pads
24
disposed thereon.
The first semiconductor chip
25
is bonded to flip-chip bonding pads
24
of the substrate
20
with solder joints while the second semiconductor chip
26
is connected to the wire-bonding pads
22
of the substrate
20
with a plurality of wires. The lower chip
25
is not impeded by the upper chip
26
due to its electrical connection to the substrate
20
by the flip-chip bonding method.
However, the circuit layout of the substrate will be relatively complicated, and the density and length of wires on the substrate will also be greatly increased. Due to the increased length of the wires, the impedance, inductance, and noise accordingly increase to affect the electrical efficiency at the final package. The increased inductance also causes the semiconductor package to consume more power and causes the integrated circuit and the wires inside the chips to easily meet power surges. In addition, due to the increased length of the wires, the wires may break easily during the wire-bonding process and cause the wire sweep during the encapsulation process. The chip-stacked package is a chip-to-substrate package, that is, the packaging process proceeds after chips are cut from the wafers such that the surfaces of the chips may be contaminated during the wafer-dicing process.
Further, the chip-stacked package employs the flip-chip method for electrically connecting the chip to the substrate, that is, solder bumps are formed on the bonding pads of the IC chip, and the IC chip is disposed on the substrate and complete the alignment of the bonding pads such that the solder balls are formed and the IC chip connects to the substrate through heat reflow process cooperating with the surface tension effect of the solder fusion. The flip-chip bonding method has the thermal mismatch problem and is a high-temperature process such that the flip-chip bonding method is not applicable for semiconductor chips which are not high temperature-resistant.
Therefore, it is needed to provide a method of manufacturing a multichip wafer-level package so as to solve the above-mentioned problems in the prior art.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a multichip package, which can complete the packaging process and electrical connection between chips in a wafer-level packaging.
It is another object of the present invention to provide a multichip package with a hermetical cavity which surrounds a semiconductor micro device so as to ensure the reliability of the semiconductor micro device.
In order to achieve the objects mentioned hereinabove, the present invention provides a wafer-level multichip package, which comprises a first chip, a second chip, a bump ring and a plurality of bumps. The first chip has a semiconductor device, a first bonding ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding ring, and a plurality of external bonding pads disposed outside the first bonding ring and electrically connected to the semiconductor device for electrically connecting to an external circuit. The second chip has an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding ring corresponding to the first bonding ring of the first chip. The bump ring is disposed between the first bonding ring of the first chip and the second bonding ring of the second chip for bonding the first and the second chips so as to form a cavity for accommodating the semiconductor device. The bumps electrically connect the internal bonding pads of the first chip to the bonding pads of the second chip.
The present invention further provides a method for manufacturing a multichip wafer-level package with a hermetical cavity, which comprises the following steps: providing a first wafer comprising a plurality of first chips wherein each first chip is spaced to one another by scribe lines and each chip has a semiconductor device, a bonding ring, a plurality of internal bonding pads disposed within the bonding ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding ring and electrically connected to the semiconductor device for electrically connecting to an external circuit; providing a second wafer comprising a plurality of second chips wherein each second chip is spaced to one another by scribe lines and each chip has a plurality of electronic device, a plurality of bonding pads electrically connected to the electronic devices and corresponding to the internal bonding pads of the first chip, and a second bonding ring corresponding to the first bonding ring of the first chip; forming a adhesion ring on the bonding ring of the first chip or the bonding ring of the second chip; forming conductive bumps on the internal
Chen Chih Lung
Kao Jen Chieh
Liau Hsing Jung
Tao Su
Yee Kuo Chung
LandOfFree
Multichip wafer-level package and method for manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multichip wafer-level package and method for manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multichip wafer-level package and method for manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3187621