Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-09-05
2004-03-16
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S502000, C712S032000
Reexamination Certificate
active
06708282
ABSTRACT:
FIELD OF INVENTION
The invention pertains to the field of synchronizing communications between components directed from a scheduler.
BACKGROUND
Many systems are designed as a plurality of communicating computational components. In order to perform computation, an individual component must receive its input data from other components. Often, this data is itself the result of computation by those components and other components. The time required to perform computation by each component is not always uniform, resulting in some data being available before other data. The early data must be stored until the later data becomes available. Only when all of the data is available can computation proceed. Coordinating the transferring, storing and computing of data is a scheduling problem.
Solving the scheduling problem is a task for the system designer. Ad-hoc uncoordinated techniques are adequate for simple systems. However, as the complexity of the system grows, these techniques become inadequate.
One solution to this problem is to create one or more schedulers that are responsible for synchronizing the components transferring, storing and computing of data. This requires that each component have a synchronizing unit responsive to the scheduler. This unit must be able to receive scheduler commands, determine when the necessary data has arrived, and initiate component computation. It must be able to do this with varying numbers of data inputs, varying arrival times of the individual data inputs and varying computational times.
SUMMARY OF THE INVENTION
A method is disclosed for synchronizing the initiation of computation when receipt of the input data can occur in an unpredictable order. A scheduler directs a component to receive input data and to begin computation upon receipt thereof. The input data and scheduler direction may arrive in any order.
In a preferred embodiment, the scheduler informs a component of the number of input data operands required for a computation. The component initiates the computation after reception of the indicated number of input data operands. The component can receive the input data operands and scheduler command in any order.
In an alternate embodiment, individual input data operands are uniquely tagged. The scheduler informs a component of the identities of the input data operands required for a computation. The component initiates the computation after reception of the identified input data operands. The component can receive the input data operands and the scheduler command in any order.
REFERENCES:
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patent: 6487369 (2002-11-01), Sato
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Drummond et al, Intelligent Browsing for Multimedia Applications, 1996 IEEE, pp. 386-389.
Choquette Jack
McCarthy Dominic Paul
Fernandez & Assoc, LLP
Heckler Thomas M.
Raza Microelectronics Inc.
Suryawanshi Suresh K
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