Electrical computers and digital processing systems: support – Computer power control
Reexamination Certificate
2000-06-01
2003-11-25
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
C713S324000
Reexamination Certificate
active
06654893
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronics. More specifically, the present invention relates to a dynamic flop design having a power down mode.
2. The Background
Dynamic flip-flops have been used in memories for many years. The advantage of using dynamic flip-flops over static flip-flops comes in the fact that they often have shorter delays, thus allowing the overall circuit to run faster. Typically dynamic flip-flops have a precharge phase and an evaluation phase.
A common problem occurs with dynamic flip-flops when static flip-flops are used to drive them. Conventional static flip-flops have uncertainty as their output signals become stable. Therefore, the time required for the static flip-flop's output signals to become stable may extend into the evaluation phase of the dynamic flip-flop being driven by it.
One solution that has been offered for this problem is to provide a flip flop with a self-shut-off mechanism.
FIG. 1
is a schematic diagram illustrating a dynamic flip-flop with a self-shut-off mechanism. The dynamic flip flop
50
includes a first input latch
52
with a shutoff circuit
54
, a second input latch
56
with a shutoff circuit
58
, and output latches
60
and
62
. The substantially identical input latches
52
,
56
are coupled to receive clock signal CK. Additionally, the first input latch
52
is coupled to receive the data input signal D. An inverter INV
1
may also be coupled to receive the data input signal D. The second input latch
56
then receives the complement of the data input signal {overscore (D)} from the inverter INV
1
.
The first input latch
52
provides an output signal to an input lead of the first output latch
60
, through an output node OUT
1
N. Similarly, the second input latch
56
provides an output signal to an input lead of the second output latch
62
, through an output node OUT
2
N. The shutoff circuits
54
and
58
have input leads connected to the output nodes, OUT
2
N and OUT
2
N, respectively. The substantially identical output latches
60
and
62
also have output leads connected to the Q and {overscore (Q)} output terminals of the dynamic flip-flop
50
.
This dynamic flip-flop operates as follows. During the logic low portion of each cycle of the clock signal CK, the dynamic flip-flop circuit
50
is in the precharge phase. The input latches
52
and
56
sample the data input signal D and the complemented data input {overscore (D)}, respectively. The input latches
52
,
56
each output the complement of its corresponding sample input signal. Consequently, if the data input signal D is at a logic high level, the first input latch
52
will output a logic low level on the output node OUT
1
N and the second input latch
56
will output a logic high level on the output node OUT
2
N. In response to the logic levels on the output nodes OUT
1
N and OUT
2
N, the output latches
60
and
62
will generate a logic high level Q output signal and a logic low level {overscore (Q)} output signal, respectively.
The input latches
52
and
56
each output the complement of its corresponding sampled input signal. Consequently, if the data input signal D is at a logic high level, the input latch
52
will output a logic low level on the output node OUT
1
N and the input latch
54
will output a logic high level on the output node OUT
2
N. In response to the logic levels on the output nodes OUT
1
N and OUT
2
N, the output latches
60
and
62
will generate a logic high level Q output signal and a logic low level {overscore (Q)} output signal, respectively.
In addition, in response to the logic low level on the output node OUT
1
N, the shutoff circuit
58
disables the input latch
56
. As a result, the shutoff circuit
58
operates to prevent the input latch
56
from sampling the complemented data input signal {overscore (D)} after the latch
56
causes the output node OUT
1
N transitions to a logic low level. Thus, the sampling window is approximately equal to the time needed by the input latch
52
to generate the logic low level on the output node OUT
1
N, plus the propagation delay of the shutoff circuit
58
. This relatively short sampling window implements “edge-triggering” because the logic level is, in effect, sampled only at the rising edge of the clock signal CK. After being disabled during the evaluation phase, the logic levels at the output leads of the latches
52
and
56
are maintained throughout the remainder of the evaluation phase.
The first input latch
52
is implemented so that once the output node OUT
1
N is discharged (i.e., when the input latch
52
receives a logic high level data input signal D), a subsequent high-to-low transition of the data input signal D does not cause the logic level at the output node OUT
1
N to change. Alternatively, the shutoff circuit
54
can also monitor the logic level on the output node OUT
1
N and disable the first input latch
52
in response to the logic level transitioning to a logic low level.
Conversely, if at the start of the evaluation phase the data input signal D is at a logic low level, the first input latch
52
will output a logic high level on the output node OUT
1
N and the second input latch
56
will output a logic low level on the output node OUT
2
N. In response to the output signals on the output nodes OUT
1
N and OUT
2
N, the output latches
60
and
62
will provide a logic low level Q output signal and a logic high level {overscore (Q)} output signal, respectively. The logic low level at the output node OUT
2
N also causes the shutoff circuit
54
to disable the first input latch
52
, thereby helping implement the edge-triggered feature of the dynamic flip-flop circuit
50
.
The input latch
52
includes p-channel transistors PC
1
and K
2
, n-channel transistors S
1
, N
1
and EVAL, and inverters INV
2
and INV
3
. The n-channel transistor S
1
and the inverters INV
2
and INV
3
implement the shutoff circuit
54
.
The p-channel transistor PC
1
has its gate coupled to receive the clock signal CK, its source coupled to a VDD voltage source (i.e, the VDD rail) and its drain connected to the output node OUT
1
N. The output node OUT
1
N is also connected to the drain of the n-channel transistor S
1
. The gate of the n-channel transistor S
1
is coupled to the output node OUT
2
N through series connected inverters INV
2
and INV
3
, where the output lead of the inverter INV
2
is connected to the gate of the n-channel transistor S
1
, and the input lead of the inverter INV
3
is connected to the output node OUT
2
N. The source of the n-channel transistor S
2
is connected to the drain of the n-channel transistor N
1
. The n-channel transistor N
1
has its gate coupled to receive the data input signal D, and its source connected to the drain of the n-channel transistor EVAL at the node CGND. The n-channel transistor EVAL has its gate coupled to receive the clock signal CK and its source coupled to a VSS voltage source (i.e., the VSS rail).
The second input latch
56
includes p-channel transistors K
1
and PC
2
, n-channel transistors S
2
and N
2
, and inverters INV
4
and INV
5
. The second input latch
56
shares the n-channel transistor EVAL with the first input latch
52
. In addition, the n-channel transistor S
2
and the inverters INV
4
and ISV
5
implement the shutoff circuit
58
. The second input latch
56
is substantially identical to the first input latch
52
, except that the second input latch
56
is implemented with the transistors PC
2
, K
1
, S
2
and N
2
in place of the transistors PC
1
, K
2
, S
1
and N
1
, and with the inverters INV
4
and INV
5
in place of the inverters INV
2
and INV
3
. In addition, the second input latch
56
receives the complemented data input signal {overscore (Q)} through the inverter INV
1
at the gate of the n-channel transistor N
2
.
The first output latch
60
includes an inverter INV
6
and a n-channel transistor N
3
. The input lead of the inverter INV
6
is connected to the output node OUT
1
N. The output lead of the inverter INV
6
is c
Hanish Marc S.
Lee Thomas
Patel Nitin
Sun Microsystems Inc.
Thelen Reid & Priest LLP
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