Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-24
2003-02-11
Crane, Sara (Department: 2811)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06519760
ABSTRACT:
1. Field of the Invention
The present invention relates to photolithography and more particularly to optical proximity correction methods used during the development of photolithography masks used to manufacture semiconductor devices.
2. Background of the Invention
Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask will generally contain a circuit pattern corresponding to an individual layer of the IC, and a projection beam of radiation will be used to image this pattern onto various target portions (each comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated, one at a time. In one type of lithographic apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus - commonly referred to as a step-and-scan apparatus - each target portion is irradiated by progressively scanning the mask pattern through the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate parallel or anti-parallel to this direction; in the case of a projection system having a magnification factor M (generally <1), the speed V at which the substrate is scanned will be a factor M times that at which the mask pattern is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat No. 6,046,792, incorporated herein by reference.
Lithographic apparatus may employ various types of projection radiation, non-limiting examples of which include ultra-violet light (“UV”) radiation (e.g., with a wavelength of 365 nm, 248 nm, 193 nm, 157 nm or 126 nm), extreme UV (“EUV”), X-rays, ion beams or electron beams. Depending on the type of radiation used and the particular design requirements of the apparatus, it may comprise a projection system having refractive, reflective or catadioptric components, and comprise vitreous elements, grazing-incidence mirrors, selective multi-layer coatings, magnetic and/or electrostatic field lenses, etc; for simplicity, such components may be loosely referred to in this text, either singly or collectively, as a “lens”.
In a manufacturing process using such a lithographic projection apparatus, a pattern in a mask is imaged onto a substrate which is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an integrated circuit (IC). Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes may be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997 ISBN 0-07-067250-4.
As semiconductor manufacturing technology is quickly pushing towards the limits of optical lithography, the state-of-the-art processes to date have regularly produced ICs with features exhibiting critical dimensions (“CDs”) which are below the exposure wavelength (“&lgr;”). A “critical dimension” of a circuit is defined as the smallest width of a feature or the smallest space between two features. For feature patterns that are designed to be smaller than &lgr;, it has been recognized that the optical proximity effect (OPE) becomes much more severe, and in fact becomes intolerable for leading edge sub-&lgr; production processes.
Optical proximity effects are a well known characteristic of optical projection exposure tools. More specifically, proximity effects occur when very closely spaced circuit patterns are lithographically transferred to a resist layer on a wafer. The light waves of the closely spaced circuit features interact, thereby distorting the final transferred pattern features. In other words, diffraction causes adjacent features to interact with each other in such a way as to produce pattern dependent variations. The magnitude of the OPE on a given feature depends on the feature's placement on the mask with respect to other features.
One of the primary problems caused by such proximity effects is an undesirable variation in feature CDs. For any leading edge semiconductor process, achieving tight control over the CDs of the features (i.e., circuit elements and interconnects) is typically the number one manufacturing goal, since this has a direct impact on wafer sort yield and speed-binning of the final product.
It has been known that the variations in the CDs of circuit features caused by OPE can be reduced by several methods. One such technique involves adjusting the illumination characteristics of the exposure tool. More specifically, by carefully selecting the ratio of the numerical aperture of the illumination condenser (“NAc”) to the numerical aperture of the imaging objective lens (“NAo”) (this ratio has been referred to as the partial coherence ratio-&sgr;), the degree of OPE can be manipulated to some extent.
In addition to using relatively incoherent illumination, such as described above, OPE can also be compensated for by “pre-correcting” the mask features. This family of techniques is generally known as optical proximity correction (OPC) techniques.
For example, in U.S. Pat. No. 5,242,770 (the '770 patent), which is hereby incorporated by reference, the method of using scattering bars (SBs) for OPC is described. The '770 patent demonstrates that the SB method is very effective for modifying isolated features so that the features behave as if the features are dense features. In so doing, the depth of focus (DOF) for the isolated features is also improved, thereby significantly increasing process latitude. Scattering bars (also known as intensity leveling bars or assist bars) are correction features (typically non-resolvable by the exposure tool) that are placed next to isolated feature edges on a mask in order to adjust the edge intensity gradients of the isolated edges. Preferably, the adjusted edge intensity gradients of the isolated edges match the edge intensity gradients of the dense feature edges, thereby causing the SB-assisted isolated features to have nearly the same width as densely nested features.
It is generally understood that the process latitude associated with dense structures is better than that associated with isolated structures under conventional illumination for large feature sizes. However, recently, more aggressive illumination schemes such as annular illumination and multipole illumination have been implemented as a means of improving resolution. When utilizing such illumination schemes, the inventors of the present invention have noted that some optical phenomenon have become more prominent. In particular, the inventors have noticed a forbidden pitch phenomena. More specifically, there are pitch ranges within which the process latitude of a “densely located” main feature, especially the exposure latitude, is worse than that of an isolated featur
Chen Jang Fung
Hsu Stephen
Shi Xuelong
ASML Masktools B.V.
Crane Sara
McDermott & Will & Emery
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