Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-27
2003-02-25
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S587000, C438S588000
Reexamination Certificate
active
06524910
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to create dual gate dielectric structures, featuring different thicknesses for the silicon oxide component of each gate dielectric structure.
(2) Description of Prior Art
The increasing integrated circuit applications featuring dual voltage capabilities, necessitate the need for a specific gate insulator thickness to satisfy each specific voltage of the circuit requirement. Therefore procedures for fabricating a silicon dioxide gate insulator layer, at a specific thickness for specific regions of a semiconductor chip, while fabricating another silicon dioxide gate insulator layer, at a different thickness, for a different region of the same semiconductor chip, is needed. One such procedure is to thermally grow a thick silicon dioxide layer on the entire semiconductor substrate followed by a patterning procedure employed to remove the thick silicon oxide layer in regions in which a subsequent thinner silicon dioxide gate insulator will be thermally grown. This procedure however places masking photoresist shapes on the surface of the portion of the thick silicon oxide layer, which will be used as the gate insulator layer for the higher voltage applications. The contamination presented by the photoresist shapes, and the possible photoresist residue remaining on the gate insulator layer after photoresist removal procedures, can deleteriously influence the integrity of the thick silicon dioxide gate insulator component of the gate structure in terms of yield and reliability.
The present invention will describe a procedure for creation of both thick and thin, silicon dioxide gate insulator layers, on the same semiconductor substrate, however without directly subjecting any portion of an existing silicon dioxide layer, to photoresist processing. This is accomplished via thermal oxidation of an underlying semiconductor substrate, through portions of overlying thin silicon nitride shapes, and through portions of overlying thick silicon nitride shapes. Prior art, such as Tsui et al, in U.S. Pat. No. 5,960,289, describe the attainment of dual gate insulator layers via thermal oxidation of a portion of bare semiconductor, resulting in a first silicon dioxide layer, while a second silicon dioxide layer is protected by a silicon nitride shape, during the oxidation procedure. This prior art however subjects the portion of the semiconductor substrate to photoresist removal procedures, prior to growth of the first silicon dioxide layer.
SUMMARY OF THE INVENTION
It is an object of this invention to form gate structures, with two different thickness of a silicon dioxide component of the gate structure, with the silicon dioxide components underlying silicon nitride components, in turn comprised with two different thickness.
It is another object of this invention to define a first silicon nitride layer on a first portion of a semiconductor substrate, followed by the deposition of a second silicon nitride layer, resulting in a composite, thick silicon nitride layer, comprised of the second, and first silicon nitride layers, overlying the first portion of the semiconductor substrate, while the thinner, second silicon nitride layer is located overlying a second portion of the semiconductor substrate.
It is still yet another object of this invention to thermally grow a thin silicon dioxide layer, through the composite silicon nitride layer, on the first portion of the semiconductor substrate, while thermally growing a thicker, second silicon dioxide layer, through the second silicon nitride layer, on the second portion of semiconductor substrate.
In accordance with the present invention a method of forming a first group of gate structures, featuring a first silicon dioxide gate insulator layer, while forming a second group of gate structures, featuring a second silicon dioxide gate insulator layer, with the thickness of the second silicon dioxide layer greater than the thickness of the first silicon dioxide gate insulator layer, is described. After deposition of a first silicon nitride layer, on a semiconductor substrate, a portion of the first silicon nitride layer is removed from the surface of a second portion of the semiconductor substrate. A second silicon nitride layer is then deposited resulting in a composite silicon nitride layer overlying a first portion of the semiconductor substrate, with the composite silicon nitride layer comprised of the second silicon nitride layer overlying the first silicon nitride layer. The second portion of the semiconductor substrate is only covered by the second silicon nitride layer. A thermal oxidation procedure next results in the growth of a thinner, first silicon dioxide layer, on the first portion of the semiconductor substrate with the oxidation rate slowed by the overlying composite silicon nitride layer. The same thermal oxidation procedure results in a thicker, second silicon dioxide layer, on the second portion of the semiconductor substrate, featuring a faster oxidation rate though the thinner, second silicon nitride layer. Deposition and patterning of a polysilicon, or polycide layer, results in: a first group of gate structures, located on the first portion of the semiconductor substrate, featuring a gate dielectric comprised of the composite silicon nitride layer on the thin, first silicon dioxide layer; and a second group of gate structures, located on the second portion of the semiconductor substrate, featuring a gate dielectric comprised of the second silicon nitride layer on the thicker, second silicon dioxide layer.
REFERENCES:
patent: 5861347 (1999-01-01), Maiti et al.
patent: 5918133 (1999-06-01), Gardner et al.
patent: 5960289 (1999-09-01), Tsui et al.
patent: 6048769 (2000-04-01), Chau
patent: 6087236 (2000-07-01), Chau et al.
Chooi Simon
Dong Zhong
Lin Wenhe
Pey Kin Leong
Zhou Mei Sheng
Chartered Semiconductor Manufacturing Ltd.
Le Dung A
Nelms David
Pike Rosemary L. S.
Saile George O.
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