Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-05
2003-11-18
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C029S846000, C029S880000, C200S264000, C361S748000
Reexamination Certificate
active
06649516
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-170018, filed Jun. 5, 2001; and No. 2001-295461, filed Sep. 27, 2001, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for manufacturing a composite member comprising an insulating body which is provided with a conductive region such as a wiring, the composite member being designed to be employed as a wiring board in various technical fields such as electrics, electronics and telecommunications.
2. Description of the Related Art
In recent years, there has been a prominent advance with regard to the integration and miniaturization of various kinds of electric and electronic parts including semiconductor devices. It is certain that this trend will further advance. Concomitant with this trend, it has been tried to make a metallic wiring finer in pattern and in pitch as well as to make a metallic wiring sterically (three-dimensionally), thereby making it also possible to realize a high-density packaging in a printed wiring board.
Among them, the three-dimensional metallic wiring is indispensable to realize high-density packaging, and therefore, there have been proposed various methods for the manufacture of a wiring board provided with a three-dimensional wiring.
According to the conventional method of manufacturing a wiring board however, it is very difficult to easily prepare a fine wiring structure which is three-dimensionally free in configuration.
In the formation of a three-dimensional wiring in a wiring board, a plurality of two-dimensional wiring boards are laminated to form a multi-layered wiring board structure as represented by a build-up wiring board for example. According to this multi-layered wiring board structure, a wiring layer is electrically connected through a conductive column of a so-called “via” with a neighboring wiring layer which is disposed thereupon or thereunder.
The via to be employed in this manner has been conventionally formed by the following procedures. First of all, by a photolithography step employing a photo-sensitive polyimide or resist, a through-hole (via-hole) is formed in an insulating body. Then, the through-hole is selectively plated or filled with a conductive paste to form the via. If the via is to be formed in this manner, various steps such as the coating of a resist to form a resist film, the exposure of the resist film, and the etching of the resist film are required. Therefore, the formation of a via is not only very troublesome but also very difficult in improving the yield thereof.
As another example of the method of forming the via, there is known a method wherein a via-hole having a predetermined size is formed in an insulating body by using a drill or a CO
2
laser, and then, a plating is applied to the via-hole or the via-hole is filled with a conductive paste to form the via.
However, it is difficult, according to the aforementioned method wherein a hole is formed in an insulating body, to form a fine via having a diameter of not more than several tens of microns at any desired region of the insulating body.
Japanese Patent Unexamined Publication (Kokai) H7-207450 discloses a method wherein a three-dimensional porous film made of PTFE is at first impregnated, through the pores thereof, with a compound having a hydrophilic group, and then, the resultant porous film is subjected to a patterning exposure by using a low pressure mercury lamp (wavelength: 185 nm and 254 nm) to form a pattern of the hydrophilic group on the three-dimensional porous film, to which a metallic plating is subsequently applied.
However, the method proposed by this Japanese Patent Publication is accompanied with various problems that the three-dimensional porous film material is caused to degrade due to the exposure using light having short wavelength, that the exposure beam is incapable of penetrating into the interior of the porous body as it is absorbed by the three-dimensional porous film to make it impossible to form a fine via, and that since most of the compounds to be impregnated into the three-dimensional porous film are liquid, measurements to cope with the spilling of liquid are required to be taken on the occasion of the exposure process.
Japanese Patent Unexamined Publication (Kokai) H10-149722 discloses another method of forming the via. According to this method, a photosensitive composition containing a photo-sensitive reducer and a metal salt is at first impregnated into the entire surface of a porous insulating body, the resultant porous insulating body is then subjected to a patterning exposure to reduce the cation of the metal salt of the exposure region into a metal nucleus, and after the photo-sensitive reducer existing in the unexposure region has been completely washed out, a electroless plating is applied to the residual metal nucleus to form a via of a desired pattern.
However, the method proposed by this Japanese Patent Publication is accompanied with various problems that since a photosensitive composition containing a metal salt is enabled to impregnate the entire surface of a porous insulating body, it is difficult to completely remove, subsequent to the exposure process, the metal salt that has been adsorbed onto the nonexposure region, thereby permitting the generation of a phenomenon of precipitating the metal nucleus at an undesired region in the subsequent reducing process, that due to this abnormal precipitation of the metal nucleus, the insulation property between neighboring vias or between neighboring wiring layers would be deteriorated as the pattern becomes increasingly finer, and that since the exposure light is absorbed by the metal salt or the metal nucleus that has been generated, it is impossible to enable the interior of the porous body to be sufficiently exposed to the exposure light.
Moreover, according to the aforementioned conventional manufacturing method of a wiring board, a wiring is formed subsequent to the formation of the via on an insulating substrate, thereby raising a problem that it is difficult to secure a sufficient contact between the via and the wiring, and hence to ensure an electric contact between them. Additionally, a misalignment may be caused to generate between the via and the wiring due to the expansion or contraction of the insulating substrate on the occasion when the wiring is to be formed on the insulating substrate after finishing the provision of the via. Therefore, it is necessary, in order to absorb this misalignment, to provide the wiring with a via-receiving portion called a “land”. Generally, since the diameter of the land is 2 to 3 times higher than the diameter of the via and since the wiring is required to be formed while keeping it away from this large land, it is difficult to enhance the density of wiring. Further, since the wiring is formed on the surface of the insulating substrate, the adhesivity between the wiring and the insulating substrate is relatively poor, thus raising a problem that a conductive portion may peel away from the insulating substrate on the occasion of mounting electronic parts thereon or in the use of electronic parts.
With a view to solve the aforementioned problems, the present inventors have proposed in Japanese Patent Application 2000-159163 a method wherein a substrate made of a porous insulating body and covered on the inner surface thereof with a photosensitive composition layer containing naphthoquinone diazide as a photo-sensitizer is subjected to a patterning exposure by using ultraviolet rays, thereby making it possible to form a conductive portion in the interior of a porous body. According to this method, since the interior of the porous body is enabled to be sufficiently exposed to ultraviolet rays, it becomes possible to form a fine via and a fine wiring.
With a view to enhance the photo-sensitivity so as to enable the exposure to be performed by using eve
Asakawa Koji
Hiraoka Toshiro
Hotta Yasuyuki
Matake Shigeru
Jr. Carl Whitehead
Kabushiki Kaisha Toshiba
Smoot Stephen W.
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