Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-09-06
2003-02-25
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C711S105000, C714S763000
Reexamination Certificate
active
06526533
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to integrated circuits, and more particularly to integrated circuits that implement internally generated commands.
Consumer electronic devices and computers are on a path of advancing power. Contributing to this advance are developments in integrated circuits, including semiconductor memories. To illustrate, in the past twenty years semiconductor memories have increased in capacity (i.e., the number of memory bits per unit) by over a thousand fold. However, capacity increases have generally not been matched by correlative improvements directed to accessing memory's storage locations, e.g., by substantial reductions in the number of cycles consumed in accessing a certain proportion of the memory's storage locations. As such, writing and/or reading to a substantial proportion of a memory—as may arise during testing and/or during certain non-test operations (e.g., graphics and other media-related)—can be undesirably slow.
Developments in semiconductor memories have been marked not only by improvements in capacity, but also by great reductions in unit cost. Unit costs are a function of the investment costs associated with building and equipping modern semiconductor facilities. Moreover, unit costs are a function of the facilities' operating costs, such operating costs typically including each of fabrication and test costs.
Fabrication generally is a batch process that provides for amortizing the investment and fabrication costs over a high volume of units and, accordingly, tends to decrease unit costs. Testing, however, tends to increase unit costs. The cost benefits of batch fabrication and the cost detriments of testing tend to apply in like character across integrated circuits.
The costs of testing generally occurs in several stages. To illustrate, testing of memory units typically is performed by the semiconductor manufacturer prior to shipping the units to system producers. Moreover, system producers may test the systems that incorporate the units, and the producers' customers may test the systems in the field. In any case, each test has an allocable cost and, therein, tends to increase the unit cost associated with the semiconductor memories.
Prior to shipment of units, the manufacturer typically tests the units in two phases. The first phase is generally referred to as “wafer probe” or “wafer sort”. This phase includes the testing the functional and/or parametric performance of the semiconductor memory as individual integrated circuits, typically while the integrated circuits are still in wafer form, i.e., before the integrated circuit has been cut apart from the wafer and while any special test pads are accessible. The second phase is typically referred to as “final test”. This phase includes the testing of functional and/or parametric performance of the semiconductor memory as individually packaged integrated circuits, typically using external pins of the circuit.
Per-unit test cost is a function of both the number of, and the cost per, testing cycle. Integrated circuits generally require numerous testing cycles in order to verify proper operation. As integrated circuits gain complexity, the number of testing cycles tends to increase. For example, with semiconductor memories the testing cycles typically are employed to write and read test data (i.e., various combinations of logical ones and zeroes) to and from storage locations of a unit under test. As the number of tested storage locations increases from its already relatively large number, the employed test cycles have tended to be increasing from an already relatively large number. Accordingly, testing of large-capacity semiconductor memories, assuming a fixed test cost per testing cycle, tends to engender a significant per-unit test cost.
Generally, statistical analysis has been employed to reduce the number of testing cycles, e.g., by reducing the number of units tested from a batch and/or by the number of storage locations tested per average unit. Even with statistics-based reductions, large and increasing memory capacities generally tend to correspond to a relatively large number of testing cycles. Beyond the statistical reductions, reduction in the number of testing cycles may be obtained by improving the process for accessing storage locations. As previously stated, such access improvements can also be desirable in certain nontest operations.
Accordingly, a need exists for methods and apparatuses for effectively accessing integrated circuits, particularly semiconductor memories.
SUMMARY OF THE INVENTION
In one aspect of the present invention, systems, circuits and methods are provided for effectively accessing integrated circuits by implementing internally generated commands associated with access.
In a more specific aspect of the present invention, systems, circuits and methods are provided that enable access of a memory's storage locations, particularly for testing, by implementing internally generated commands to reduce the clock cycles associated with performing certain access sequences. The number of clock cycles are reduced, broadly, by reducing the number of external control signals (and eliminating provision of such signals' associated address information) engendered by access sequences. These external control signals are replaced by certain internally generated commands which are (i) generated concurrently with certain commands issued responsive to external control signals and (ii) communicated via data paths distinct from such issued commands so as to preclude resource conflict there between. The address information associated with such internally generated commands preferably is determined from the address information associated with one or more of the remaining external control signals.
In one embodiment of the present invention, the apparatus includes (a) a command generator that internally generates one or more commands in place of commands that otherwise might be issued responsive to external control signals, (b) a command coordinator that coordinates such generated commands with issued commands, the issued commands being issued responsive to external control signals and (c) an m-dimensional structure of redundant circuits that are accessible individually or in groups. The embodiment further comprises, in another aspect, a mode register for enabling one or more modes, including a mode which employs internal generation of commands.
The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this specification. For a better understanding of the invention, its operating advantages and specific objects attained by its use, reference should be made to the accompanying drawings and descriptive matter in which its preferred embodiments are illustrated and described, wherein like reference numerals identify the same or similar elements.
REFERENCES:
patent: 6032220 (2000-02-01), Martin et al.
patent: 6192446 (2001-02-01), Mullarkey
Cowles Timothy B.
Wright Jeffery P.
Chung Phung M.
Micro)n Technology, Inc.
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