4. Static information storage and retrieval
  5. Read/write circuit
  6. Testing

Jeffery P. Wright

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Integrated circuit implementing internally generated commands

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Semiconductor memory implementing internally generated commands

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Testing parameters of an electronic device

Static information storage and retrieval – Read/write circuit – Testing
Patent

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Profile ID: LFUS-PAI-P-1612544

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