Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
1999-12-17
2003-02-04
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S774000, C118S724000, C432S131000
Reexamination Certificate
active
06514879
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor structures and manufacturing. More particularly, the invention relates to extremely thin dielectric layers and the methods and apparatus for the formation thereof.
2. Background
Advances in semiconductor manufacturing technology have led to the integration of millions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to integrate increasing numbers of circuit elements onto an integrated circuit it has been necessary to reduce the line widths of the various parts that make up an integrated circuit. Not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors (MOSFETs).
MOSFETs are also sometimes referred to as insulated gate field effect transistors (IGFETs). Most commonly, these devices are referred to simply as FETs, and are so referred to in this disclosure.
Transistor scaling typically involves more than just the linear reduction of the FET width and length. For example, both source/drain (S/D) junction depth and gate dielectric thickness are also typically reduced in order to produce a FET with the desired electrical characteristics.
Over the years, a substantial amount of research and development in the field semiconductor manufacturing has been dedicated to providing reduced thickness dielectric layers, as mentioned above. However, to be suitable for use as a MOSFET gate dielectric layer, these reduced thickness dielectric layers are typically required to provide certain electrical characteristics. For example, the dielectric layer should have a low density of interface states, a low density of defects, and a dielectric breakdown voltage high enough for use with the desired voltages that the MOSFET will encounter during operation. Furthermore, such a reduced thickness dielectric layer should be manufacturable with great uniformity and repeatability.
What is needed is an extremely thin dielectric layer suitable for use as the gate dielectric layer in a MOSFET, and what is further needed are apparatus and methods for repeatably making such ultra-thin dielectric layers.
SUMMARY OF THE INVENTION
Briefly, a configuration of various chemical compound generators coupled to a furnace provides the environment suitable for repeatably forming extremely thin oxides of silicon on a wafer with a high degree of uniformity.
In a further aspect of the present invention, MOSFETs having gate dielectric layers of extremely thin oxides of silicon are formed.
REFERENCES:
patent: 5127365 (1992-07-01), Koyama et al.
patent: 5234501 (1993-08-01), Nakao et al.
patent: 5595605 (1997-01-01), Tai et al.
patent: 5599425 (1997-02-01), Lagendijk et al.
patent: 5763922 (1998-06-01), Chau
patent: 6093662 (2000-07-01), Ohmi et al.
Tanabe et al. Diluted wet oxidation: a novel technique for ultra thin gate oxide formation, IEEE Semiconductor Manufacturing Conference Proceedings, pp. 49-52, Oct. 1997.
Arghavani Reza
Chau Robert
Dalesky Ron
Blakely , Sokoloff, Taylor & Zafman LLP
Chaudhuri Olik
Intel Corporation
Kielin Erik
LandOfFree
Method and apparatus for dry/catalytic-wet steam oxidation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for dry/catalytic-wet steam oxidation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for dry/catalytic-wet steam oxidation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3169052