Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
1999-04-09
2003-06-03
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
06574776
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to processing of data information in an error control procedure.
BACKGROUND OF THE INVENTION
In parity-based error control procedures that are presently used, data representing a “bare” message, without error control bytes attached thereto, are read from memory three times: once to calculate an error detection control (EDC) segment, once to calculate a P-parity checkbyte, and once to calculate a Q-parity checkbyte. Each read operation requires a certain time increment, and this triple reading of each data byte adds substantially to the total time required to perform error detection and correction procedures on a given data block.
What is needed is an approach that reduces the number of times a given array of data elements must be read from memory, without substantially increasing the time required for subsequent processing of the data for error control purposes. Preferably, the approach should be flexible enough to allow each data element received to be used for more than one computation and should not require that the error control procedures be performed in a particular order. Preferably, the approach should extend to data element arrays of arbitrary size.
SUMMARY OF THE INVENTION
These needs are met by the invention, which provides a modified procedure for using an array of data elements, each read once from memory, received separately at an EDC processor and at an ECC P-parity processor, and processed in parallel in the two processors to compute an EDC error detection term and, simultaneously, to compute two ECC P-parity syndromes s
0
and s
1
. A first procedure is used at the EDC processor to compute the EDC term by receiving the sequence {s(k)} of data elements (k=0, 1, . . . , 1117) in serial order and computing the EDC factor as the data elements are received. A second procedure is used in parallel at the ECC processor to compute components of the two ECC syndromes as the data elements are received in serial order. Because the two processors operate independently but in parallel, the time required for combined EDC and ECC processing is approximately half of what would otherwise be required, and each data element s(k) need only be read once from memory.
REFERENCES:
patent: 4413339 (1983-11-01), Riggle et al.
patent: 4555784 (1985-11-01), Wood
patent: 4951284 (1990-08-01), Abdel-Ghaffar et al.
patent: 5361266 (1994-11-01), Kodama et al.
patent: 5577054 (1996-11-01), Pharris
Kuo et al. (Concurrent error detection and correction in real-time systolic sorting arrays; IEEE, On pp.: 1615-1620, Dec. 1992).*
Cosentino, R.J (Concurrent error correction in systolic architectures; IEEE, On pp.: 117-125, Jan. 1988).*
Parallel error-trapping and error-detection decoding;—Lee, P. Chang, S.; IEEE, pp.: 35-38 vol. 1; Nov. 4-6, 1991.
De'cady Albert
Lamarre Guy
Oak Technology, Inc.
Schipper John F.
LandOfFree
Simultaneous processing for error detection and P-parity ECC... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Simultaneous processing for error detection and P-parity ECC..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simultaneous processing for error detection and P-parity ECC... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3162178