Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
1999-09-01
2003-06-17
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S289000, C438S197000
Reexamination Certificate
active
06579751
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to semiconductor processing methods of forming integrated circuitry, and particularly to methods of forming integrated circuit devices having different threshold voltages.
BACKGROUND OF THE INVENTION
Field effect transistors are characterized by a source region, a drain region and a gate. The source and drain regions are typically received within a semiconductive material, such as a semiconductive substrate. The gate is typically disposed elevationally over the source and drain regions. A gate voltage of sufficient minimum magnitude can be placed on the gate to induce a channel region underneath the gate and between the source and drain regions. Such channel-inducing voltage is typically referred to as the transistor's threshold voltage, or V
t
. Accordingly, the threshold voltage turns the transistor on. Once the magnitude of the threshold voltage has been exceeded, current can flow between the source and drain regions in accordance with a voltage called the source/drain voltage, or V
ds
.
Threshold voltage magnitudes can be affected by channel implants. Specifically, during fabrication of semiconductor devices, a substrate can be implanted with certain types of impurity to modify or change the threshold voltage of a resultant device. Such channel implants can also affect a condition known as subsurface punchthrough. Punchthrough is a phenomenon which is associated with a merging of the source and drain depletion regions within a MOSFET. Specifically, as the channel gets shorter (as device dimensions get smaller), depletion region edges get closer together. When the channel length is decreased to roughly the sum of the two junction depletion widths, punchthrough is established. Punchthrough is an undesired effect in MOSFETS.
One way of addressing punchthrough in sub-micron devices is through provision of a so-called halo implant, also known as a “pocket” implant. Halo implants are formed by implanting dopants (opposite in type to that of the source and drain) within the substrate proximate the source and drain regions, and are typically disposed underneath the channel region. The implanted halo dopant raises the doping concentration only on the inside walls of the source/drain junctions, so that the channel length can be decreased without needing to use a higher doped substrate. That is, punchthrough does not set in until a shorter channel length because of the halo.
It is desirable to have MOSFETS with different threshold voltages depending upon the context in which the integrated circuitry of which they comprise a part is to be used. In the context of memory devices it can be beneficial to have transistors with different threshold voltages.
This invention arose out of concerns associated with improving the methods through which integrated circuits are fabricated. In particular, the invention arose concerns associated with providing improved methods of forming memory devices.
SUMMARY OF THE INVENTION
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.
REFERENCES:
patent: 4612629 (1986-09-01), Harari
patent: 4785342 (1988-11-01), Yamanaka et al.
patent: 5272367 (1993-12-01), Dennison et al.
patent: 5534449 (1996-07-01), Dennison et al.
patent: 5661054 (1997-08-01), Kauffman et al.
patent: 5683927 (1997-11-01), Dennison et al.
patent: 5736444 (1998-04-01), Kauffman et al.
patent: 5747855 (1998-05-01), Dennison et al.
patent: 5773863 (1998-06-01), Burr et al.
patent: 5776806 (1998-07-01), Dennison et al.
patent: 5786249 (1998-07-01), Dennison
patent: 6004854 (1999-12-01), Dennison et al.
patent: 6074924 (2000-06-01), Dennison et al.
patent: 6124616 (2000-09-01), Dennison et al.
patent: 6312997 (2001-11-01), Tran
patent: 6337250 (2002-01-01), Furuhata
patent: 6455362 (2002-09-01), Tran et al.
patent: 0717448 (1999-04-01), None
PCT Application WO 98/29897 Thompson et al, Jul. 1998.*
Silicon Processing for the VLSI Era, vol. III; “Punchthrough(Subsurface-DIBL)in Short-Channel MOSFETs”; undated; pp. 232-235, 238-244.
Chaudhari Chandra
Schillinger Laura M
Wells St. John P.S.
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