Semiconductor device having transistor

Details Semiconductor device having transistor Semiconductor device having transistor

2001-11-14

2003-06-10

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S346000, C257S387000, C257S389000, C257S412000, C257S413000, C257S900000

Reexamination Certificate

active

06576963

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-28692, filed May 24, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a transistor and a method of manufacturing the same.
2. Description of the Related Art
Transistors, which are elements determining the electrical characteristics of a semiconductor device, have gate electrodes formed on a semiconductor substrate and source and drain regions formed in the semiconductor substrate and aligned on both sides of the gate electrodes. In order to insulate the gate electrodes from the source and drain regions, the transistor adopts spacers which are formed of a dielectric material at the sidewalls of the gate electrodes. These dielectric spacers serve as an ion implantation mask classifying heavily doped source/drain regions and lightly doped source/drain regions in a transistor having a lightly doped drain (LDD) structure. The spacers are formed of silicon oxide or silicon nitride.
However, as the integration density of semiconductor devices increases and in particular, the length of gate electrodes becomes 0.18 &mgr;m or less, the size of contact holes for connecting bit lines to source/drain regions and connecting storage electrodes to source/drain regions decreases and a margin for forming the contact holes decreases. Thus, the spacers are formed at the sidewalls of the gate electrodes of a material having an excellent etching selectivity to an interlevel dielectric layer filled inbetween the gate electrodes, thereby proposing a technique of forming the contact holes by a self-aligned method (hereinafter, referred to as a method of forming self-aligned contact holes). In general, a silicon oxide layer is used as an interlevel dielectric layer and a silicon nitride layer is used for dielectric spacers in the method of forming self-aligned contact holes.
A method of forming self-aligned contact holes according to the prior art will be described with reference to
FIGS. 1A through 1C
.
FIG. 1A
is a plan view of a semiconductor device having a transistor where self-aligned contact holes are formed, and
FIGS. 1B and 1C
are cross-sectional views taken along lines I—I and II—II, respectively, of FIG.
1
A.
Gate oxide layers (not shown), gate electrodes formed of polysilicon patterns
12
and tungsten or tungsten silicide patterns
14
, and silicon nitride-layer patterns
16
are sequentially formed on a semiconductor substrate
10
. Spacers
18
are formed of silicon nitride at the sidewalls of the gate electrodes and the silicon nitride layer patterns
16
. Etch stoppers
20
and
22
are formed of silicon nitride at the sidewalls of the spacers
18
or on the semiconductor substrate
10
. Source and drain regions
30
are formed inbetween gate electrodes in the semiconductor substrate
10
. A contact hole
26
b
for a plug that electrically connects bit lines (not shown) to the source/drain regions
30
and contact holes
26
a
and
26
c
for plugs that electrically connects storage electrodes to the source/drain regions
30
are self-aligned and formed by a method using spacers
18
formed of silicon nitride and having an excellent etching selectivity of an interlevel dielectric layer
24
filled inbetween gate electrodes. The etch stoppers
20
and
22
prevent the semiconductor substrate
10
from being damaged when removing the interlevel dielectric layer
24
between the gate electrodes. However, the etch stopper
22
remains on the semiconductor substrate
10
in
FIG. 1C
where the interlevel dielectric layer
24
is not removed.
The dielectric constant of silicon oxide is 4, and the dielectric constant of silicon nitride is 7. Since spacers formed at the sidewalls of gate electrodes contact source/drain regions, the resistance-capacitance (RC) of a transistor adopting spacers formed of silicon nitride is high, thereby decreasing the operational speed of semiconductor devices.
Currently, a method of forming self-aligned contact holes is applied only to a cell area but may be applied to a peripheral circuit area if the integration density is increased. Thus, a problem of decreasing the operation speed of a row decoder, a column decoder, and a sense amplifier formed in the peripheral circuit area may be expected.
As a result, an attempt to form spacers of SiC, which has a low dielectric constant, was made. However, in a case of using SiC spacers, a process of manufacturing transistors having SiC spacers can only be developed after fully grasping the operational characteristics of semiconductor devices including changes in operational characteristics of transistors due to SiC.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is a first object of the present invention to provide a semiconductor device having a transistor which can inhibit an increase of RC and a method of manufacturing the same using an existing process of manufacturing the semiconductor device in which spacers are formed of silicon nitride.
It is a second object of the present invention to provide a semiconductor device having a transistor and a method of manufacturing the same to which a method of forming self-aligned contact holes can be applied.
According to an aspect of the present invention, to achieve the first and second objects of the present invention, there is provided a semiconductor device. The semiconductor device includes a portion having gate electrodes, etch mask layers, spacers formed of a material having a low dielectric constant at sidewalls of the gate electrodes and the etch mask layers, and transistors having source/drain regions formed in the semiconductor substrate and inbetween the gate electrodes; and another portion having conductive patterns and an interlevel dielectric layer formed of a material having an excellent etching selectivity to the etch mask layers to fill spaces inbetween the conductive patterns. The gate electrodes may be formed of polysilicon and tungsten or tungsten silicide formed on the polysilicon. The conductive patterns are formed of the same material as the gate electrodes, and a dielectric layer may be formed on the conductive patterns of the same material as the etch mask layers. Thus, the spacers at the sidewalls of the gate electrodes are formed of a material having a dielectric constant, e.g., silicon oxide, thereby inhibiting an increase in RC of the semiconductor device. The etch mask layers have an excellent etching selectivity to the interlevel dielectric layer. Thus, a semiconductor substrate on the source/drain regions, which will be filled with a conductive material to form a contact plug, may be exposed by a self-alignment-method. For example, the interlevel dielectric layer may be a silicon oxide layer, and the etch mask layers may be silicon nitride layers. In order to prevent damage to the semiconductor substrate exposed in a process of forming self-aligned contact holes, the semiconductor device may include an etch stopper formed between the sidewalls of the gate electrodes and the etch mask layers and the spacers, on the surface and side of the interlevel dielectric layer, on sides of the conductive patterns, and between the interlevel dielectric layer and the semiconductor substrate. The etch stopper is formed of a material having an excellent etching selectivity to the interlevel dielectric layer, e.g., silicon nitride.
According to another aspect of the present invention, to achieve the first and second objects of the present invention, there is provided a semiconductor device. The semiconductor device includes: a semiconductor substrate having a cell area and a peripheral circuit area; gate electrodes and etch mask layers sequentially formed in the cell area and the peripheral circuit area in the semiconductor substrate; spacers formed of a material having a l

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