Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-24
2003-06-03
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S908000
Reexamination Certificate
active
06573574
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and manufacturing method therefor, and more particularly, to a cell array region of a NOR-type mask ROM device and a fabricating method therefor.
2. Description of the Related Art
In semiconductor memory devices, mask ROM devices are characterized in that information programmed in a memory cell is not erasable, nor is new information storable in a specific cell. The mask ROMs have a relatively simple fabricating process, as compared with flash memory devices. They can be used for example in applications where a user desires a code to be stored, and can be manufactured within a relatively short time. A method of programming the mask ROMs is to selectively implant impurities into the channel region of a desired cell during their manufacture in such a way as to change the threshold voltage of the desired cell.
FIG. 1
is a plan view showing a portion of a cell array region in a conventional NOR-type mask ROM. Referring to
FIG. 1
, a plurality of sub-bit lines SBL
1
, SBL
2
, SBL
3
, SBL
4
, . . . , comprised of a buried N
+
layer, are arranged parallel to one another on a semiconductor substrate. A plurality of word lines WL
1
, WL
2
, WL
3
, . . . which intersect the sub-bit lines SBL
1
, SBL
2
, SBL
3
, SBL
4
, . . . at right angles, are arranged parallel to each other. In addition, a plurality of bit lines BL
1
, BL
2
, . . . are formed parallel to the sub-bit lines SBL
1
, SBL
2
, SBL
3
, and SBL
4
. The bit lines BL
1
, BL
2
, . . . are connected to the sub-bit lines through a select transistor to transmit an external electrical signal. In particular, the sub-bit lines SBL
1
, SBL
2
, SBL
3
, SBL
4
, . . . operate as a source/drain of a memory cell transistor. The region between the sub-bit lines SBL
1
, SBL
2
, SBL
3
, SBL
4
, . . . disposed in the lower part of the word lines is used as a channel region. The word lines WL
1
, WL
2
, WL
3
, . . . are formed on the source/drain region and channel region to operate as gate electrodes.
FIGS. 2A
,
3
A and
4
A are sectional views for explaining a method for fabricating a conventional NOR-type mask ROM cell taken along line A-A′ shown in
FIG. 1
, while
FIGS. 2B
,
3
B and
4
B are sectional views for explaining a method of fabricating the same taken along line B-B′ shown in FIG.
1
. Referring to
FIGS. 2A and 2B
, a P-well region
13
is formed over a semiconductor substrate
11
. A sacrificial oxide layer
15
, is provided over the surface of the P-well region
1
, and on top of the sacrificial oxide layer
15
a first photoresist pattern
17
is formed using a photo mask in which the sub-bit lines of
FIG. 1
are drawn. Then, N-type impurities
19
such as arsenic (As) are implanted on the surface of the P-well region
13
using the first photoresist pattern
17
as an ion implantation mask, to form a plurality of N-type impurity regions
21
parallel to one another.
Referring to
3
A and
3
B, the first photoresist pattern
17
and the sacrificial oxide layer
15
are removed to expose the plurality of N-type impurity regions
21
formed on or on the surface of the P-well region
13
. Then, a gate oxide layer
23
such as a thermal oxide layer is formed on the surface of the resulting material. Consequently, impurities within the N-type impurity regions
21
are activated to form a plurality of buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
, which are parallel to one another. In this case, impurities within the N-type impurity regions
21
are diffused along the boundary between the gate oxide layer
23
and the P-well region
13
to form tails (TL) on the edges of each of the buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
. This is because, when the gate oxide layer, i.e. thermal oxide layer, is formed with the N-type impurity regions
21
exposed, the speed at which impurities within the N-type impurity regions
21
are diffused into the bulk region of the P-well region
13
is faster than the speed at which the same impurities are diffused along the surface of the P-well region
13
. This phenomenon is referred to as the “oxidation enhanced diffusion” effect. This makes the gap between the plurality of buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
narrower than the original gap between the N-type impurity regions
21
. As a result, some problems occur in that the width of an isolation area as well as the effective channel length of cell transistors is reduced since the gap between buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
operating as a source/drain region is narrower.
Furthermore, the plurality of buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
serve as common source and drain lines of cell transistors. Thus, it is preferable that the plurality of buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
are doped to as high a concentration as possible, in order to reduce their resistance. However, as the concentration of impurities in the plurality of buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
becomes higher, the tails (TL) become longer and the effective channel of cell transistors becomes shorter.
Additionally, at the initial stage of a thermal oxidation process for forming the gate oxide layer
23
, an out-diffusion of impurities, i.e., arsenic ions, within the N-type impurity regions
21
occurs. This causes the out-diffused N-type impurities to be moved again on the surfaces of the P-well region
13
and a substrate of the peripheral circuit region (not shown), which may locally change the concentration of impurities on the substrate surfaces. If the impurity concentration on the substrate surfaces turns out to be uneven, an electrical characteristic such as the threshold voltage of an MOS transistor will also be uneven, so that malfunction of the circuit occurs.
A first conductive layer (not shown) such as a doped polysilicon layer is provided on top of the gate oxide layer
23
. The first conductive layer is patterned to form a plurality of word lines (WL
2
)
25
which intersect the plurality of buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
at right angles. Next, on the substrate over which the plurality of word lines
25
is formed, a second photoresist pattern
26
, which opens the desired cell using a program mask shown in
FIG. 1
, is formed. Then, P-type impurities
27
such as boron (B) ions are implanted selectively on the channel region of the desired cell, using the second photoresist pattern
26
as an ion implantation mask. The channel concentration of the desired cell is higher than the original channel concentration, so that the threshold voltage of the desired cell is increased. As a result, the desired cell is programmed.
Referring to
FIGS. 4A and 4B
, the second photoresist pattern
26
is removed. A interlayer insulating layer
28
is provided over the entire surface of the semiconductor substrate
11
from which the second photoresist pattern
26
has been removed. Then, bit line contact holes (not shown) which expose a predetermined region among the buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
are formed, patterning the interlayer insulating layer
28
. A second conductive layer (not shown), e.g., a metal layer is provided over the entire of the semiconductor substrate
11
on which the bit line contact holes have been formed. A plurality of bit lines BL
1
and BL
2
which intersect the plurality of word lines
25
at right angles are formed by patterning the second conductive layer. First and second bit lines BL
1
and BL
2
are each electrically connected to the N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
through the bit line contact holes.
As described above, according to the conventional art, tails (TL) occur when a plurality of buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
are formed on the surface of a semiconductor substrate. As a result, the gap between the buried N
+
layers SBL
1
, SBL
2
, SBL
3
, and SBL
4
become
Fahmy Wael
Mills & Onello LLP
Pham Hoai
Samsung Electronics Co,. Ltd.
LandOfFree
Cell array region of a NOR-type mask ROM device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cell array region of a NOR-type mask ROM device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cell array region of a NOR-type mask ROM device and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3158907