Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-20
2003-10-28
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000
Reexamination Certificate
active
06638817
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a DRAM cell array which does not require a device isolation layer between cells and a fabrication method thereof.
2. Description of the Conventional Art
Presently, with an increase of memory capacity of Dynamic Random Access Memory(DRAM), the area of a memory device being integrated on a wafer is being reduced, and the area occupied by a transistor and a capacitor is also being reduced at a predetermined ratio.
The basic element of a semiconductor memory circuit is a memory device capable of storing bit of data, that is, a cell. DRAM comprises a plurality of cells, each all being formed of a transistor and a capacitor, and a peripheral circuit capable of reading and writing data onto the cells.
FIGS. 1
a
to
1
c
are views showing a conventional DRAM cell array.
FIG. 1
a
is a plan view of a DRAM cell array,
FIG. 1
b
is an equivalent circuit diagram of
FIGS. 1
a,
and
FIG. 1
c
is a cross-sectional view taken along line C—C of
FIG. 1
a.
Referring to
FIG. 1
a
and
1
c,
in the conventional DRAM cell array, a semiconductor substrate
1
includes isolation regions
1
b
and a plurality of active regions
1
a
in a rectangular island shape formed at a predetermined distance from each other. A plurality of transistors
3
are formed on the active regions
1
a,
and a field oxide film
2
is formed on the isolation regions
1
b.
Transistors
3
each include a plurality of gate electrodes
3
b
formed by interleaving a gate insulating film
3
a
on the substrate
1
, and a source
3
c
and drain
3
d
region formed of n-type dopant in the substrate
1
at both sides of the gate electrodes
3
b.
As shown therein, two transistors
3
in the active region
1
a
are connected in series.
In the gate electrodes
3
b,
polysilicon in a rectangular strip shape at a predetermined distance from each other is deposited in a direction vertical to the arrangement of the active regions
1
a,
and the gate electrodes serve as word lines
9
.
A first interlayer insulating film
5
which has contact holes
5
a
exposing one of the source
3
c
and drain
3
d
regions of the transistors
3
is formed on the entire surface of the substrate
1
and transistors
3
.
A plurality of capacitors
6
are formed on the first interlayer insulating film
5
. The capacitors
6
each include a lower electrode
6
a
formed on an upper surface of the first interlayer insulating film
5
and in the contact holes
5
a
in a fin structure, and an upper electrode
6
c
formed by interleaving a capacitor insulating film
6
b
on the lower electrode
6
a.
A plurality of bit lines
8
selectively connected to one of the source
3
c
and drain
3
d
regions of the transistors
3
are arranged in parallel, and a plurality of word lines
9
selectively connecting the gate electrodes
3
b
of the transistors
3
are arranged in parallel so as to be vertical to the arrangement of the bit lines
8
. The bit lines
8
are connected selectively with one of the source
3
c
and drain
3
d
regions of the transistor
3
via bit line contact holes
7
a
of a second interlayer insulating film
7
.
A device isolation insulating film, that is, a field oxide film
2
is formed on the semiconductor substrate
1
between the neighboring transistors in a direction that the bit lines
8
are arranged.
The read/write operation of the above-described conventional DRAM cell array will be explained as follows.
When a high voltage is applied to the word lines
9
and bit lines
8
, a corresponding transistor is turned on, thereby forming a data charge transmission path(channel) on a lower part of the gate region. The data charges transmitted from the bit lines
8
are transmitted to a storage electrode forming the lower electrode
6
a
of the capacitor
6
through source regions
3
c,
channels, and drain regions
3
d.
In addition, in order to read each bit, a sensor amplifier(not shown) measures the amount of charges flowing into the capacitors
6
, and decides whether a data charge is stored in the capacitor
6
(that is, ‘0’ state) or not(that is, ‘1’ state). Then, the capacitor
6
is refreshed by fully filling the charges or emptying the same again.
The above-described conventional DRAM cell array has the following problems.
First, as the degree of integration of a memory device increases, the area of the active regions accepting each transistor becomes smaller, and thereby the shape of the active regions formed on the substrate becomes close to a circular form due to the technical problems in photolithography and etching process.
Second, as the area of wiring lines and capacitors connected with the active regions decreases, misalignments such as an over-contact arise, resulting in the decrease in the reliability of the device.
Third, the active regions are formed in a form of island, and the isolation regions needed for implementing an insulation between the active regions occupy a lot of space on the substrate, so that there is a difficulty in enhancing the degree of integration of the device.
SUMMARY OF THE INVENTION
Accordingly, to solve the above problems, it is an object of the present invention to define active regions on a substrate in a strip form to thereby minimize the area occupied by isolation regions, and provide a DRAM cell array that improve the degree of integration of a memory device by implementing an insulation between transistors formed in the active regions through additional word lines.
To achieve the above object, a DRAM cell array according to the present invention is characterized by the structure which includes: a semiconductor substrate on which a plurality of active regions and isolation regions are formed in a rectangular strip shape at a predetermined distance; a plurality of transistors each having a gate electrode formed by interleaving a gate insulating film on the active regions and a source and drain region formed in the substrate at both sides of the gate electrodes; a plurality of capacitors connected with one of the source and drain regions of the plurality of transistors and having a lower electrode and a upper electrode formed by interleaving a capacitor insulating film on the lower electrode, and a plurality of bit lines connected with one of the source and drain regions of the plurality of transistors and arranged in parallel; and a plurality of word lines formed of first word lines and second word lines vertical to the direction in which the bit lines are arranged.
Also, to achieve the above-described object, there is provided a fabrication method for a DRAM cell array according to the present invention which includes: defining active regions and isolation regions in a rectangular strip shape at a predetermined space on a semiconductor substrate; forming a plurality of gate electrodes which have interleaved a gate insulating film on the active regions; forming a source and drain region in the substrate at both sides of the gate electrodes in order to form a plurality of transistors; forming a plurality of lower electrodes connected with one of the source and drain regions of the transistors on the substrate on which the transistors are formed; forming an upper electrode interleaved by a capacitor insulating film on the lower electrode in order to form a plurality of capacitors; forming a plurality of bit lines in parallel connected with one of the source and drain regions of the transistors on the substrate on which the capacitors are formed; and forming a plurality of word lines formed of first word lines and second word lines which are vertical to the direction in which the bit lines are arranged and selectively connected with the gate electrodes
32
of the transistors
30
.
REFERENCES:
patent: 5591998 (1997-01-01), Kimura et al.
patent: 5663092 (1997-09-01), Lee
patent: 5903026 (1999-05-01), Gonzalez
patent: 5930621 (1999-07-01), Kang et al.
patent: 6008085 (1999-12-01), Sung et al.
patent: 6074918 (2000-06-01), Lee
patent: 6150689 (2000-11-
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
Pham Hoai
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