Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-07-05
2003-10-21
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C714S719000, C365S201000, C365S189070
Reexamination Certificate
active
06636998
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device and a parallel bit test method thereof capable of accurate detection of defective memory cells at the time of performing a parallel bit test.
2. Description of the Background Art
A conventional semiconductor memory device prepares for a parallel bit test in response to a test mode setting command at the time of performing the test. If a write command is applied from a tester, the semiconductor memory device writes test pattern data supplied by the tester to a memory cell array. If a read command is generated by the tester, the semiconductor memory device reads data from the memory cell array. Following this, the memory device compares two data elements read from the memory cell array and detects whether the comparison result indicates that the data are identical with each other, and outputs the result to the tester.
However, the conventional parallel bit test requires that two identical test pattern data bits be written to and read from each pair of memory cells during application of the test pattern data. In addition, the memory device requires that the pairs of read test pattern data elements are compared with each other, and the comparison result is output to the tester.
For example, in the case where the memory device writes identical data to two memory cells among four memory cells in the memory cell array, and compares two data output from the four memory cells in pairs of two by two; if the two data are identical with each other, the memory cells are determined to be normal. If the two data are different, the memory cells are determined to be defective. That is, the memory device produces one comparison result in comparing the four data bits. If the memory cells are determined to be defective by the comparison result, the four memory cells are replaced with redundant memory cells.
In this test configuration, in the case where each of two memory cells into which the identical data is written are defective and two data output from the memory cells are identical with each other, the memory cells are determined not to be defective, but instead determined to be normal. For example, if data stored as “11” are all read as “00” since both of two memory cells are defective, the memory cells are determined to be normal even though the memory cells are actually defective.
Accordingly, the parallel bit test method for conventional semiconductor memory device can not input various test patterns to the device for testing memory cells. In the event that all memory cells in which identical data are stored are defective, the resulting comparison data will incorrectly indicate that the cells are non-defective.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor memory device which can correctly detect the existence of defective memory cells as well as enable a test using various test patterns.
Another object of the present invention is to provide a parallel bit test method of a semiconductor memory device for achieving the above-mentioned object.
According to a first aspect, the present invention is directed to a semiconductor memory device. The device comprises a memory cell array having a plurality of memory cells for storing data upon an externally applied write command and for retrieving data upon an externally applied read command. An address generator stores data to, and retrieves data from, the memory cells of said memory cell array, in response to an externally applied address. A pattern data register stores externally-applied pattern data to be written to and retrieved from the memory cells as said data according to said externally applied address, and outputs pattern data during retrieval of said data from said memory cells. A comparator compares the retrieved data from the memory cells with the corresponding pattern data, and generates test result data as a result of the comparison.
The semiconductor memory device may further comprising a test mode setting register for receiving an externally applied test mode setting command and said externally applied data, and, in response, initiating a bit test. The comparator may comprise a plurality of exclusive OR gates, each for comparing elements of said retrieved data with corresponding elements of said pattern data to generate intermediate comparison data, and an OR gate for performing an OR operation on the intermediate comparison data to generate said test result data.
The pattern data register may output said pattern data as said data to be written to said memory cell array, or, optionally, the test pattern data to be written to the memory cell array may be externally applied.
In a second aspect, the present invention is directed to a method for testing a semiconductor memory device having a memory cell array including a plurality of memory cells for storing data upon an externally applied write command and for retrieving data upon an externally applied read command. The method comprises applying a test mode command to the memory device; storing data corresponding to predetermined pattern data in the memory cells of said memory cell array in response to an externally applied address;
retrieving data from the memory cells in response to the externally applied address; and comparing the retrieved data from the memory cells with the corresponding pattern data, and generating test result data as a result of the comparison.
The method of the present invention may further comprise the step of receiving the externally applied test mode command and, in response, initiating a bit test. The step of comparing may be performed at a comparator comprising: a plurality of exclusive OR gates, each for comparing elements of said retrieved data with corresponding elements of said pattern data to generate intermediate comparison data; and an OR gate for performing an OR operation on the intermediate comparison data to generate said test result data. The predetermined pattern data may be stored in a register, or optionally, may be externally applied in a write operation.
REFERENCES:
patent: 5241501 (1993-08-01), Tanaka
patent: 5917764 (1999-06-01), Ohsawa et al.
Kim Myeong O
Lee Jae Woong
Mills & Onello LLP
Moise Emmanuel L.
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