Programmable logic array with vertical transistors

Electronic digital logic circuitry – Multifunctional or programmable – Array

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S102000

Reexamination Certificate

active

06515510

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuits in particular to a programmable logic array with vertical transistors.
BACKGROUND OF THE INVENTION
Logic circuits are an integral part of digital systems, such as computers. Essentially, a logic circuit processes a number of inputs to produce a number of outputs for use by the digital system. The inputs and outputs are generally electronic signals that take on one of two “binary” values, a “high” logic value or a “low” logic value. The logic circuit manipulates the inputs using binary logic which describes, in a mathematical way, a given or desired relationship between the inputs and the outputs of the logic circuit.
Logic circuits that are tailored to the specific needs of a particular customer can be very expensive to fabricate on a commercial basis. Thus, general purpose very large scale integration (VLSI) circuits are defined. VLSI circuits serve as many logic roles as possible, which helps to consolidate desired logic functions. However, random logic circuits are still required to tie the various elements of a digital system together.
Several schemes are used to implement these random logic circuits. One solution is standard logic, such as transistor-transistor logic (TTL). TTL integrated circuits are versatile because they integrate only a relatively small number of commonly used logic functions. The drawback is that large numbers of TTL integrated circuits are typically required for a specific application. This increases the consumption of power and board space, and drives up the overall cost of the digital system.
One alternative to standard logic is fully custom logic integrated circuits. Custom logic circuits are precisely tailored to the needs of a specific application. This allows the implementation of specific circuit architectures that dramatically reduces the number of parts required for a system. However, custom logic devices require significantly greater engineering time and effort, which increases the cost to develop these circuits and may also delay the production of the end system.
A less expensive alternative to custom logic is the “programmable logic array.” Programmable logic arrays take advantage of the fact that complex combinational logic functions can be reduced and simplified into various standard forms. For example, logical functions can be manipulated and reduced down to traditional Sum of Products (SOP) form. In SOP form, a logical function uses just two types of logic functions that are implemented sequentially. This is referred to as two-level logic and can be implemented with various conventional logic functions, e.g., AND-OR, NAND-NAND, NOR-NOR.
One benefit of the programmable logic array is that it provides a regular, systematic approach to the design of random, combinational logic circuits. A multitude of logical functions can be created from a common building block, e.g., an array of transistors. The logic array is customized or “programmed” by creating a specific metallization pattern to interconnect the various transistors in the array to implement the desired function.
Programmable logic arrays are fabricated using photolithographic techniques that allow semiconductor and other materials to be manipulated to form integrated circuits as is known in the art. These photolithographic techniques essentially use light that is focused through lenses and masks to define patterns in the materials with microscopic dimensions. The equipment and techniques that are used to implement this photolithography provide a limit for the size of the circuits that can be formed with the materials. Essentially, at some point, the lithography cannot create a fine enough image with sufficient clarity to decrease the size of the elements of the circuit. In other words, there is a minimum dimension that can be achieved through conventional photolithography. This minimum dimension is referred to as the “critical dimension” (CD) or minimum “feature size” (F) of thee photolithographic process. The minimum feature size imposes one constraint on the size of the components of a programmable logic array. In order to keep up with the demands for larger programmable logic arrays, designers search for ways to reduce the size of the components of the array.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a programmable logic array that uses less surface area of a semiconductor wafer as compared to conventional arrays.
SUMMARY OF THE INVENTION
The above mentioned problems with programmable logic arrays and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A programmable logic array is described which is formed with vertical transistors.
In one embodiment, a programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane also includes a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.


REFERENCES:
patent: 3657575 (1972-04-01), Taniguchi et al.
patent: 3806741 (1974-04-01), Smith
patent: 3931617 (1976-01-01), Russell
patent: 4020364 (1977-04-01), Kuijk
patent: 4051354 (1977-09-01), Choate
patent: 4252579 (1981-02-01), Ho et al.
patent: 4313106 (1982-01-01), Hsu
patent: 4604162 (1986-08-01), Sobczak
patent: 4617649 (1986-10-01), Kyomasu et al.
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4663831 (1987-05-01), Birrittella et al.
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4677589 (1987-06-01), Haskell et al.
patent: 4701423 (1987-10-01), Szluk
patent: 4716314 (1987-12-01), Mulder et al.
patent: 4740826 (1988-04-01), Chatterjee
patent: 4761385 (1988-08-01), Pfiester
patent: 4761768 (1988-08-01), Turner et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4845537 (1989-07-01), Nishimura et al.
patent: 4888735 (1989-12-01), Lee et al.
patent: 4906590 (1990-03-01), Kanetaki et al.
patent: 4920065 (1990-04-01), Chin et al.
patent: 4920515 (1990-04-01), Obata
patent: 4929988 (1990-05-01), Yoshikawa
patent: 4949138 (1990-08-01), Nishimura
patent: 4958318 (1990-09-01), Harari
patent: 4965651 (1990-10-01), Wagner
patent: 4987089 (1991-01-01), Roberts
patent: 5001526 (1991-03-01), Gotou
patent: 5006909 (1991-04-01), Kosa
patent: 5010386 (1991-04-01), Groover, III
patent: 5017504 (1991-05-01), Nishimura et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5028977 (1991-07-01), Kenneth et al.
patent: 5057896 (1991-10-01), Gotou
patent: 5072269 (1991-12-01), Hieda
patent: 5083047 (1992-01-01), Horie et al.
patent: 5087581 (1992-02-01), Rodder
patent: 5102817 (1992-04-01), Chatterjee et al.
patent: 5107459 (1992-04-01), Chu et al.
patent: 5110752 (1992-05-01), Lu
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5140388 (1992-08-01), Bartelink
patent: 5156987 (1992-10-01), Sandhu et al.
patent: 5177028 (1993-01-01), Manning
patent: 5177576 (1993-01-01), Kimura et al.
patent: 5181089 (1993-01-01), Matsuo et al.
patent: 5191509 (1993-03-01), Wen
patent: 5202278 (1993-04-01), Mathews et al.
patent: 5208657 (1993-05-01), Chatterjee et al.
patent: 5216266 (1993-06-01), Ozaki
patent: 5221867 (1993-06-01), Mitra et al.
patent: 5223081 (1993-06-01), Doan
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5276343 (1994-01-01), Kumagi et al.
patent: 5292676 (1994-03-01), Manning
patent: 5308782 (1994-05-01), Mazure et al.
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 5320880 (1994-06-01), Sandhu et al.
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5329481 (1

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programmable logic array with vertical transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic array with vertical transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic array with vertical transistors will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3153242

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.